Searched refs:controller (Results 176 - 200 of 629) sorted by relevance

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/linux-master/drivers/clk/sunxi-ng/
H A Dccu_reset.c9 #include <linux/reset-controller.h>
/linux-master/drivers/reset/tegra/
H A Dreset-bpmp.c6 #include <linux/reset-controller.h>
/linux-master/drivers/pci/hotplug/
H A Dshpchp_core.c63 static int init_slots(struct controller *ctrl)
129 void cleanup_slots(struct controller *ctrl)
257 struct controller *ctrl;
305 struct controller *ctrl = pci_get_drvdata(dev);
/linux-master/drivers/soc/fsl/qe/
H A Dgpio.c144 struct qe_gpio_chip *controller; member in struct:qe_pin
192 qe_pin->controller = gpiochip_get_data(gc);
237 struct qe_gpio_chip *qe_gc = qe_pin->controller;
281 struct qe_gpio_chip *qe_gc = qe_pin->controller;
/linux-master/drivers/mtd/nand/raw/
H A Darasan-nand-controller.c133 * @read: Data transfer direction from the controller point of view
168 * of the controller structure @gpio_cs array
193 * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
198 * @controller: Base controller structure
199 * @chips: List of all NAND chips attached to the controller
214 struct nand_controller controller; member in struct:arasan_nfc
231 return container_of(ctrl, struct arasan_nfc, controller);
338 struct arasan_nfc *nfc = to_anfc(chip->controller);
344 /* Update the controller timing
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H A Ddenali_dt.c22 struct denali_controller controller; member in struct:denali_dt
124 denali = &dt->controller;
186 * will cause unpredictable behavior in the controller.
239 denali_remove(&dt->controller);
259 MODULE_DESCRIPTION("DT driver for Denali NAND controller");
H A Dmarvell_nand.c3 * Marvell NAND flash controller driver
9 * This NAND controller driver handles two versions of the hardware,
26 * controller when Hamming is chosen:
36 * 30B per ECC chunk. Here is the page layout used by the controller
56 * The controller has certain limitations that are handled by the
66 * - The controller will always treat data bytes, free OOB bytes
112 /* System control registers/bits to enable the NAND controller on some SoCs */
124 /* NAND controller data flash control register */
166 /* NAND controller status register */
181 /* NAND controller dat
407 struct nand_controller controller; member in struct:marvell_nfc
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H A Dtxx9ndfmc.c3 * TXx9 NAND flash memory controller driver
72 struct nand_controller controller; member in struct:txx9ndfmc_drvdata
309 nand_controller_init(&drvdata->controller);
310 drvdata->controller.ops = &txx9ndfmc_controller_ops;
336 chip->controller = &drvdata->controller;
417 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
H A Dcadence-nand-controller.c3 * Cadence NAND flash controller driver
45 * of the NF controller.
126 /* Enable controller ECC check bits generation and correction. */
159 /* Available hardware features of the controller. */
400 /* Operation the controller needs to perform. */
435 /* Cadence NAND flash controller capabilities get from driver data. */
443 /* Cadence NAND flash controller capabilities read from registers. */
457 struct nand_controller controller; member in struct:cdns_nand_ctrl
546 cdns_nand_ctrl *to_cdns_nand_ctrl(struct nand_controller *controller) argument
548 return container_of(controller, struc
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H A Dtegra_nand.c170 struct nand_controller controller; member in struct:tegra_nand_controller
195 return container_of(hw_ctrl, struct tegra_nand_controller, controller);
316 dev_err(ctrl->dev, "Tegra NAND controller register dump\n");
355 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
464 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
500 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
659 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
705 * E.g. controller might return fail_sec_flag with 0x4, which
769 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
822 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
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H A Dsunxi_nand.c185 * @ecc: ECC controller structure
209 * NAND Controller capabilities structure: stores NAND controller capabilities
224 * struct sunxi_nfc - stores sunxi NAND controller information
226 * @controller: base controller structure
228 * @regs: NAND controller registers
229 * @ahb_clk: NAND controller AHB clock
230 * @mod_clk: NAND controller mod clock
231 * @reset: NAND controller reset line
233 * @clk_rate: NAND controller curren
241 struct nand_controller controller; member in struct:sunxi_nfc
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/linux-master/net/devlink/
H A Dport.c246 attrs->pci_pf.controller) ||
254 attrs->pci_vf.controller) ||
263 attrs->pci_sf.controller) ||
925 new_attrs.controller =
1378 * @controller: associated controller number for the devlink port instance
1380 * @external: indicates if the port is for an external controller
1382 void devlink_port_attrs_pci_pf_set(struct devlink_port *devlink_port, u32 controller, argument
1394 attrs->pci_pf.controller = controller;
1409 devlink_port_attrs_pci_vf_set(struct devlink_port *devlink_port, u32 controller, u16 pf, u16 vf, bool external) argument
1437 devlink_port_attrs_pci_sf_set(struct devlink_port *devlink_port, u32 controller, u16 pf, u32 sf, bool external) argument
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/linux-master/drivers/clk/meson/
H A Dmeson-aoclk.c14 #include <linux/reset-controller.h>
69 dev_err(dev, "failed to register reset controller\n");
/linux-master/drivers/char/tpm/
H A Dtpm_tis_spi_main.c76 * Half duplex controller with support for TPM wait state detection like
78 * control. Each phase sent in different transfer for controller to idenity
150 spi_bus_lock(phy->spi_device->controller);
214 spi_bus_unlock(phy->spi_device->controller);
222 struct spi_controller *ctlr = phy->spi_device->controller;
226 * Send entire message to a half duplex controller to handle
227 * wait polling in controller.
277 if (dev->controller->flags & SPI_CONTROLLER_HALF_DUPLEX)
/linux-master/drivers/usb/host/
H A Dohci-pci.c74 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
136 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
241 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
244 if (hcd->self.controller) {
269 .product_desc = "OHCI PCI host controller",
274 /* handle any USB OHCI controller */
H A Dehci-fsl.c31 #define DRIVER_DESC "Freescale EHCI Host controller driver"
45 * Allocates basic resources for this USB host controller.
112 /* Enable USB controller, 83xx or 8536 */
120 /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
127 * controller reset for USB Controller version 2.5
143 device_wakeup_enable(hcd->self.controller);
198 struct device *dev = hcd->self.controller;
202 dev_warn(hcd->self.controller, "Could not get controller version\n");
212 /* controller versio
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H A Dmax3421-hcd.c10 * controller on a SPI bus.
344 struct spi_device *spi = to_spi_device(hcd->self.controller);
369 struct spi_device *spi = to_spi_device(hcd->self.controller);
393 struct spi_device *spi = to_spi_device(hcd->self.controller);
419 struct spi_device *spi = to_spi_device(hcd->self.controller);
525 struct spi_device *spi = to_spi_device(hcd->self.controller);
631 struct spi_device *spi = to_spi_device(hcd->self.controller);
766 struct spi_device *spi = to_spi_device(hcd->self.controller);
846 struct spi_device *spi = to_spi_device(hcd->self.controller);
935 struct spi_device *spi = to_spi_device(hcd->self.controller);
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/linux-master/drivers/spi/
H A Dspi-mem.c22 * @ctlr: the SPI controller requesting this dma_map()
30 * Only SPI controller drivers should use it.
64 * @ctlr: the SPI controller requesting this dma_unmap()
74 * controller drivers should use it.
167 struct spi_controller *ctlr = mem->spi->controller;
230 struct spi_controller *ctlr = mem->spi->controller;
239 * spi_mem_supports_op() - Check if a memory device and the controller it is
245 * support specific opcodes, or it can even be that the controller and device
264 struct spi_controller *ctlr = mem->spi->controller;
291 struct spi_controller *ctlr = mem->spi->controller;
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H A Dspi-gpio.c29 * spi->controller->dev.driver_data ... points to spi_gpio->bitbang
80 bang = spi_controller_get_devdata(spi->controller);
173 * call when such pin is not present or defined in the controller.
183 flags = spi->controller->flags;
193 flags = spi->controller->flags;
203 flags = spi->controller->flags;
213 flags = spi->controller->flags;
307 * functions associated with a "native" SPI controller if a driver for that
308 * controller is not available, or is missing important functionality.
H A Dspi-wpcm-fiu.c152 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
197 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
242 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
279 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
354 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
377 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
401 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
505 MODULE_DESCRIPTION("Nuvoton WPCM450 FIU SPI controller driver");
H A Dspi-fsl-spi.c3 * Freescale SPI controller driver.
91 struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller);
186 mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
254 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
345 static int fsl_spi_transfer_one(struct spi_controller *controller, argument
362 static int fsl_spi_unprepare_message(struct spi_controller *controller, argument
387 mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
481 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
600 /* SPI controller initializations */
H A Dspi-omap2-mcspi.c3 * OMAP2 McSPI controller driver
121 /* Virtual base address of the controller */
241 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
244 /* The controller handles the inverted chip selects
307 struct spi_controller *ctlr = spi->controller;
394 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
406 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
423 mcspi = spi_controller_get_devdata(spi->controller);
461 mcspi = spi_controller_get_devdata(spi->controller);
606 mcspi = spi_controller_get_devdata(spi->controller);
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/linux-master/drivers/usb/musb/
H A Dmusb_trace.h30 __string(name, dev_name(musb->controller))
44 __string(name, dev_name(musb->controller))
157 __string(name, dev_name(musb->controller))
178 __string(name, dev_name(musb->controller))
318 __string(name, dev_name(ch->hw_ep->musb->controller))
/linux-master/drivers/ata/
H A Dpata_legacy.c3 * pata-legacy.c - Legacy port PATA/SATA controller driver.
127 enum controller { enum
148 enum controller type;
157 enum controller type;
193 enum controller type, unsigned long private)
282 * This controller supports PIO0 to PIO2. We set PIO timings
284 * support is weird being DMA to controller and PIO'd to the host
381 * This controller supports PIO0 to PIO2 (no IORDY even though higher
413 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
479 * This controller support
972 struct legacy_controller *controller = &controllers[probe->type]; local
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/linux-master/drivers/iio/adc/
H A Dad_sigma_delta.c215 spi_bus_lock(sigma_delta->spi->controller);
238 spi_bus_unlock(sigma_delta->spi->controller);
290 spi_bus_lock(sigma_delta->spi->controller);
325 spi_bus_unlock(sigma_delta->spi->controller);
390 spi_bus_lock(sigma_delta->spi->controller);
404 spi_bus_unlock(sigma_delta->spi->controller);
429 return spi_bus_unlock(sigma_delta->spi->controller);

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