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f693b648 |
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26-Sep-2023 |
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> |
mtd: rawnand: arasan: Include ECC syndrome along with in-band data while checking for ECC failure Following an ECC failure condition upon page reads, we shall distinguish between a real ECC failure and an empty page. This is handled with a call to nand_check_erased_ecc_chunk() which looks at the data and counts the number of bits which are not 'ones'. If we get less zeros than the ECC strength, we assume the page was erased and we are in the presence of natural bitflips. Otherwise, if we are above, we assume some data was written and the ECC engine could not recover it all, so we report an ECC failure. In order for this logic to be as close as the reality as we can (this is already a simplified condition but we can hardly be more precise), we should check all the data that is covered by the ECC step not only the in-band data, so we should also include the ECC syndrome in the check. Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine") Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230927055621.2906454-1-amit.kumar-mahapatra@amd.com
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3a4a893d |
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17-Jul-2023 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Ensure program page operations are successful The NAND core complies with the ONFI specification, which itself mentions that after any program or erase operation, a status check should be performed to see whether the operation was finished *and* successful. The NAND core offers helpers to finish a page write (sending the "PAGE PROG" command, waiting for the NAND chip to be ready again, and checking the operation status). But in some cases, advanced controller drivers might want to optimize this and craft their own page write helper to leverage additional hardware capabilities, thus not always using the core facilities. Some drivers, like this one, do not use the core helper to finish a page write because the final cycles are automatically managed by the hardware. In this case, the additional care must be taken to manually perform the final status check. Let's read the NAND chip status at the end of the page write helper and return -EIO upon error. Cc: Michal Simek <michal.simek@amd.com> Cc: stable@vger.kernel.org Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/linux-mtd/20230717194221.229778-2-miquel.raynal@bootlin.com
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a36201ac |
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20-Aug-2023 |
Li Zetao <lizetao1@huawei.com> |
mtd: rawnand: arasan: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "disable_bus_clk" and "disable_controller_clk". Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Li Zetao <lizetao1@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-3-lizetao1@huawei.com
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21962132 |
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06-Jun-2023 |
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> |
Revert "mtd: rawnand: arasan: Prevent an unsupported configuration" This reverts commit fc9e18f9e987ad46722dad53adab1c12148c213c. This patch was a work around to fix timeout issue while operating in NVDDR mode with software ECC engine. This patch prevents the Arasan NAND driver from operating in NVDDR mode with software ECC engine resulting in a significant performance degradation with SW-ECC. 'commit 7499bfeedb47 ("mtd: rawnand: arasan: Update NAND bus clock instead of system clock")' and 'commit e16eceea863b ("mtd: rawnand: arasan: Fix clock rate in NV-DDR")' fixes the timeout issue in NVDDR mode with SW-ECC so, reverting the changes as this work around is no longer required. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230607053936.14306-1-amit.kumar-mahapatra@amd.com
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ec185b18 |
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11-Apr-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
mtd: nand: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> # atmel Reviewed-by: Paul Cercueil <paul@crapouillou.net> # ingenic Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> # ingenic Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> # intel Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> # meson Acked-by: Roger Quadros <rogerq@kernel.org> # omap_elm Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Reviewed-by: Heiko Stuebner <heiko@sntech.de> # rockchip Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> # sunxi Acked-by: Thierry Reding <treding@nvidia.com> # tegra Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230411113816.3472237-1-u.kleine-koenig@pengutronix.de
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37ea9f16 |
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25-Jul-2022 |
GONG, Ruiqi <gongruiqi1@huawei.com> |
mtd: rawnand: arasan: stop using 0 as NULL pointer Fix the following sparse warnings: drivers/mtd/nand/raw/arasan-nand-controller.c:918:70: warning: Using plain integer as NULL pointer drivers/mtd/nand/raw/arasan-nand-controller.c:918:73: warning: Using plain integer as NULL pointer Signed-off-by: GONG, Ruiqi <gongruiqi1@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220725112108.686347-1-gongruiqi1@huawei.com
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e16eceea |
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28-Jun-2022 |
Olga Kitaina <okitain@gmail.com> |
mtd: rawnand: arasan: Fix clock rate in NV-DDR According to the Arasan NAND controller spec, the flash clock rate for SDR must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the CLK line for the mode. The driver previously always set 100 MHz for NV-DDR, which would result in incorrect behavior for NV-DDR modes 0-4. The appropriate clock rate can be calculated from the NV-DDR timing parameters as 1/tCK, or for rates measured in picoseconds, 10^12 / nand_nvddr_timings->tCK_min. Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller") CC: stable@vger.kernel.org # 5.8+ Signed-off-by: Olga Kitaina <okitain@gmail.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com
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7499bfee |
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28-Jun-2022 |
Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> |
mtd: rawnand: arasan: Update NAND bus clock instead of system clock In current implementation the Arasan NAND driver is updating the system clock(i.e., anand->clk) in accordance to the timing modes (i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be updated instead. This patch keeps the system clock unchanged and updates the NAND bus clock as per the timing modes. Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller") CC: stable@vger.kernel.org # 5.8+ Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220628154824.12222-2-amit.kumar-mahapatra@xilinx.com
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fc9e18f9 |
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08-Oct-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Prevent an unsupported configuration Under the following conditions: * after rounding up by 4 the number of bytes to transfer (this is related to the controller's internal constraints), * if this (rounded) amount of data is situated beyond the end of the device, * and only in NV-DDR mode, the Arasan NAND controller timeouts. This currently can happen in a particular helper used when picking software ECC algorithms. Let's prevent this situation by refusing to use the NV-DDR interface with software engines. Fixes: 4edde6031458 ("mtd: rawnand: arasan: Support NV-DDR interface") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211008163640.1753821-1-miquel.raynal@bootlin.com
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76e12c10 |
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27-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Finer grain NV-DDR configuration Add support for the timings register which may improve a bit the overall throughput. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084959.208804-2-miquel.raynal@bootlin.com
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23739c34 |
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27-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Rename the data interface register There are 2 timing registers: - "data interface" - "timings" So far, the "data interface" register was named "timings" which begins misleading when bringing support for the "timings" register. Rename it to "data_iface". Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084959.208804-1-miquel.raynal@bootlin.com
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cf67edce |
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27-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Use the right DMA mask Xilinx ZynqMP SoC and the Arasan controller support 64-bit DMA addressing. Define the right mask otherwise the default is 32 and some accesses may overflow the default mask. Reported-by: Jorge Courett <jorge.courett@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Jorge Courett <jorge.courett@gmail.com> Link: https://lore.kernel.org/linux-mtd/20210527084548.208429-1-miquel.raynal@bootlin.com
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acbd3d09 |
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26-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Leverage additional GPIO CS Make use of the cs-gpios DT property as well as the core helper to parse it so that the Arasan controller driver can now assert many more chips than natively. The Arasan controller has an internal limitation: RB0 is tied to CS0 and RB1 is tied to CS1. Hence, it is possible to use external GPIOs as long as one or the other native CS is not used (or configured to be driven as a GPIO) and that all additional CS are physically wired on its corresponding RB line. Eg. CS0 is used as a native CS, CS1 is not used as native CS and may be used as a GPIO CS, CS2 is an additional GPIO CS. Then the target asserted by CS0 should also be wired to RB0, while the targets asserted by CS1 and CS2 should be wired to RB1. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-5-miquel.raynal@bootlin.com
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b5437c7b |
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26-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Ensure proper configuration for the asserted target The controller being always asserting one CS or the other, there is no need to actually select the right target before doing a page read/write. However, the anfc_select_target() helper actually also changes the timing configuration and clock in the case were two different NAND chips with different timing requirements would be used. In this situation, we must ensure proper configuration of the controller by calling it. As a consequence of this change, the anfc_select_target() helper is being moved earlier in the driver. Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-4-miquel.raynal@bootlin.com
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4edde603 |
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05-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Support NV-DDR interface Add support for the NV-DDR interface. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-23-miquel.raynal@bootlin.com
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10938a08 |
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05-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Workaround a misbehaving prog type with NV-DDR As explained in the comment introduced above the fix, the Arasan controller driver starts an operation when the prog register is being written with a "type" specific to the action to perform. The prog type used until now to perform a CHANGE READ COLUMN with an SDR interface was the PAGE READ type (CMD + ADDR + CMD + DATA). Unfortunately, for an unknown reason (let's call this a silicon bug) any CHANGE READ COLUMN performed this way in NV-DDR mode will fail: the data ready flag will never be triggered, nor will be the transfer complete flag. Forcefully, this leads to a timeout situation which is not easy to handle. Fortunately, it was spotted that sending the same commands through a different prog register "type", CHANGE READ COLUMN ENHANCED, would work all the time (even though this particular command is not supported by the core and is only available in a limited set of devices - we only care about the controller configuration and not the actual command which is sent to the device). So let's use this type instead when a CHANGE READ COLUMN is requested. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-22-miquel.raynal@bootlin.com
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698ddeb8 |
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05-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Fix a macro parameter This macro is not yet being used so the compilers never complained about it. Fix the macro before using it. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-21-miquel.raynal@bootlin.com
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4dd7ef97 |
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05-May-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Check the proposed data interface is supported Check the data interface is supported in ->setup_interface() before acknowledging the timings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-3-miquel.raynal@bootlin.com
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b489681b |
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09-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
mtd: rawnand: arasan: Document 'anfc_op's 'buf' member Fixes the following W=1 kernel build warning(s): drivers/mtd/nand/raw/arasan-nand-controller.c:133: warning: Function parameter or member 'buf' not described in 'anfc_op' Cc: Naga Sureshkumar Relli <nagasure@xilinx.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Choudary Kalluri <punnaia@xilinx.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20201109182206.3037326-22-lee.jones@linaro.org
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1e3b37aa |
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27-Aug-2020 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: Use the ECC framework OOB layouts No need to have our own in the raw NAND core. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-18-miquel.raynal@bootlin.com
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bace41f8 |
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27-Aug-2020 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: Use the new ECC engine type enumeration Mechanical switch from the legacy "mode" enumeration to the new "engine type" enumeration in drivers and board files. The device tree parsing is also updated to return the new enumeration from the old strings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-11-miquel.raynal@bootlin.com
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e0a564ae |
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27-Aug-2020 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: Rename the ECC algorithm enumeration items NAND_ECC_ is not a meaningful prefix, use NAND_ECC_ALGO_ instead. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-3-miquel.raynal@bootlin.com
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4c46667b |
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29-May-2020 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: s/data_interface/interface_config/ The name/suffix data_interface is a bit misleading in that the field or functions actually represent a configuration that can be applied by the controller/chip. Let's rename all fields/functions/hooks that are worth renaming. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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88ffef1b |
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19-May-2020 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Support the hardware BCH ECC engine Add support for the hardware ECC BCH engine. Please mind that this engine has an important limitation: BCH implementation does not inform the user when an uncorrectable ECC error occurs. To workaround this, we avoid using the hardware engine in the read path and do the computation with the software BCH implementation, which is faster than mixing hardware (for correction) and software (for verification). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-9-miquel.raynal@bootlin.com
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197b88fe |
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19-May-2020 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: rawnand: arasan: Add new Arasan NAND controller Add the Arasan NAND controller driver. This brings only NAND controller support. The ECC engine being a bit subtle, hardware ECC support will be added in a second time. This work is based on contributions from Naga Sureshkumar Relli. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-8-miquel.raynal@bootlin.com
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