1// SPDX-License-Identifier: GPL-2.0 2// Copyright (C) 2022 Jonathan Neusch��fer 3 4#include <linux/clk.h> 5#include <linux/mfd/syscon.h> 6#include <linux/mod_devicetable.h> 7#include <linux/module.h> 8#include <linux/platform_device.h> 9#include <linux/regmap.h> 10#include <linux/spi/spi-mem.h> 11 12#define FIU_CFG 0x00 13#define FIU_BURST_BFG 0x01 14#define FIU_RESP_CFG 0x02 15#define FIU_CFBB_PROT 0x03 16#define FIU_FWIN1_LOW 0x04 17#define FIU_FWIN1_HIGH 0x06 18#define FIU_FWIN2_LOW 0x08 19#define FIU_FWIN2_HIGH 0x0a 20#define FIU_FWIN3_LOW 0x0c 21#define FIU_FWIN3_HIGH 0x0e 22#define FIU_PROT_LOCK 0x10 23#define FIU_PROT_CLEAR 0x11 24#define FIU_SPI_FL_CFG 0x14 25#define FIU_UMA_CODE 0x16 26#define FIU_UMA_AB0 0x17 27#define FIU_UMA_AB1 0x18 28#define FIU_UMA_AB2 0x19 29#define FIU_UMA_DB0 0x1a 30#define FIU_UMA_DB1 0x1b 31#define FIU_UMA_DB2 0x1c 32#define FIU_UMA_DB3 0x1d 33#define FIU_UMA_CTS 0x1e 34#define FIU_UMA_ECTS 0x1f 35 36#define FIU_BURST_CFG_R16 3 37 38#define FIU_UMA_CTS_D_SIZE(x) (x) 39#define FIU_UMA_CTS_A_SIZE BIT(3) 40#define FIU_UMA_CTS_WR BIT(4) 41#define FIU_UMA_CTS_CS(x) ((x) << 5) 42#define FIU_UMA_CTS_EXEC_DONE BIT(7) 43 44#define SHM_FLASH_SIZE 0x02 45#define SHM_FLASH_SIZE_STALL_HOST BIT(6) 46 47/* 48 * I observed a typical wait time of 16 iterations for a UMA transfer to 49 * finish, so this should be a safe limit. 50 */ 51#define UMA_WAIT_ITERATIONS 100 52 53/* The memory-mapped view of flash is 16 MiB long */ 54#define MAX_MEMORY_SIZE_PER_CS (16 << 20) 55#define MAX_MEMORY_SIZE_TOTAL (4 * MAX_MEMORY_SIZE_PER_CS) 56 57struct wpcm_fiu_spi { 58 struct device *dev; 59 struct clk *clk; 60 void __iomem *regs; 61 void __iomem *memory; 62 size_t memory_size; 63 struct regmap *shm_regmap; 64}; 65 66static void wpcm_fiu_set_opcode(struct wpcm_fiu_spi *fiu, u8 opcode) 67{ 68 writeb(opcode, fiu->regs + FIU_UMA_CODE); 69} 70 71static void wpcm_fiu_set_addr(struct wpcm_fiu_spi *fiu, u32 addr) 72{ 73 writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0); 74 writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1); 75 writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2); 76} 77 78static void wpcm_fiu_set_data(struct wpcm_fiu_spi *fiu, const u8 *data, unsigned int nbytes) 79{ 80 int i; 81 82 for (i = 0; i < nbytes; i++) 83 writeb(data[i], fiu->regs + FIU_UMA_DB0 + i); 84} 85 86static void wpcm_fiu_get_data(struct wpcm_fiu_spi *fiu, u8 *data, unsigned int nbytes) 87{ 88 int i; 89 90 for (i = 0; i < nbytes; i++) 91 data[i] = readb(fiu->regs + FIU_UMA_DB0 + i); 92} 93 94/* 95 * Perform a UMA (User Mode Access) operation, i.e. a software-controlled SPI transfer. 96 */ 97static int wpcm_fiu_do_uma(struct wpcm_fiu_spi *fiu, unsigned int cs, 98 bool use_addr, bool write, int data_bytes) 99{ 100 int i = 0; 101 u8 cts = FIU_UMA_CTS_EXEC_DONE | FIU_UMA_CTS_CS(cs); 102 103 if (use_addr) 104 cts |= FIU_UMA_CTS_A_SIZE; 105 if (write) 106 cts |= FIU_UMA_CTS_WR; 107 cts |= FIU_UMA_CTS_D_SIZE(data_bytes); 108 109 writeb(cts, fiu->regs + FIU_UMA_CTS); 110 111 for (i = 0; i < UMA_WAIT_ITERATIONS; i++) 112 if (!(readb(fiu->regs + FIU_UMA_CTS) & FIU_UMA_CTS_EXEC_DONE)) 113 return 0; 114 115 dev_info(fiu->dev, "UMA transfer has not finished in %d iterations\n", UMA_WAIT_ITERATIONS); 116 return -EIO; 117} 118 119static void wpcm_fiu_ects_assert(struct wpcm_fiu_spi *fiu, unsigned int cs) 120{ 121 u8 ects = readb(fiu->regs + FIU_UMA_ECTS); 122 123 ects &= ~BIT(cs); 124 writeb(ects, fiu->regs + FIU_UMA_ECTS); 125} 126 127static void wpcm_fiu_ects_deassert(struct wpcm_fiu_spi *fiu, unsigned int cs) 128{ 129 u8 ects = readb(fiu->regs + FIU_UMA_ECTS); 130 131 ects |= BIT(cs); 132 writeb(ects, fiu->regs + FIU_UMA_ECTS); 133} 134 135struct wpcm_fiu_op_shape { 136 bool (*match)(const struct spi_mem_op *op); 137 int (*exec)(struct spi_mem *mem, const struct spi_mem_op *op); 138}; 139 140static bool wpcm_fiu_normal_match(const struct spi_mem_op *op) 141{ 142 // Opcode 0x0b (FAST READ) is treated differently in hardware 143 if (op->cmd.opcode == 0x0b) 144 return false; 145 146 return (op->addr.nbytes == 0 || op->addr.nbytes == 3) && 147 op->dummy.nbytes == 0 && op->data.nbytes <= 4; 148} 149 150static int wpcm_fiu_normal_exec(struct spi_mem *mem, const struct spi_mem_op *op) 151{ 152 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); 153 int ret; 154 155 wpcm_fiu_set_opcode(fiu, op->cmd.opcode); 156 wpcm_fiu_set_addr(fiu, op->addr.val); 157 if (op->data.dir == SPI_MEM_DATA_OUT) 158 wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes); 159 160 ret = wpcm_fiu_do_uma(fiu, spi_get_chipselect(mem->spi, 0), op->addr.nbytes == 3, 161 op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes); 162 163 if (op->data.dir == SPI_MEM_DATA_IN) 164 wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); 165 166 return ret; 167} 168 169static bool wpcm_fiu_fast_read_match(const struct spi_mem_op *op) 170{ 171 return op->cmd.opcode == 0x0b && op->addr.nbytes == 3 && 172 op->dummy.nbytes == 1 && 173 op->data.nbytes >= 1 && op->data.nbytes <= 4 && 174 op->data.dir == SPI_MEM_DATA_IN; 175} 176 177static int wpcm_fiu_fast_read_exec(struct spi_mem *mem, const struct spi_mem_op *op) 178{ 179 return -EINVAL; 180} 181 182/* 183 * 4-byte addressing. 184 * 185 * Flash view: [ C A A A A D D D D] 186 * bytes: 13 aa bb cc dd -> 5a a5 f0 0f 187 * FIU's view: [ C A A A][ C D D D D] 188 * FIU mode: [ read/write][ read ] 189 */ 190static bool wpcm_fiu_4ba_match(const struct spi_mem_op *op) 191{ 192 return op->addr.nbytes == 4 && op->dummy.nbytes == 0 && op->data.nbytes <= 4; 193} 194 195static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op) 196{ 197 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); 198 int cs = spi_get_chipselect(mem->spi, 0); 199 200 wpcm_fiu_ects_assert(fiu, cs); 201 202 wpcm_fiu_set_opcode(fiu, op->cmd.opcode); 203 wpcm_fiu_set_addr(fiu, op->addr.val >> 8); 204 wpcm_fiu_do_uma(fiu, cs, true, false, 0); 205 206 wpcm_fiu_set_opcode(fiu, op->addr.val & 0xff); 207 wpcm_fiu_set_addr(fiu, 0); 208 if (op->data.dir == SPI_MEM_DATA_OUT) 209 wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes); 210 wpcm_fiu_do_uma(fiu, cs, false, op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes); 211 212 wpcm_fiu_ects_deassert(fiu, cs); 213 214 if (op->data.dir == SPI_MEM_DATA_IN) 215 wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); 216 217 return 0; 218} 219 220/* 221 * RDID (Read Identification) needs special handling because Linux expects to 222 * be able to read 6 ID bytes and FIU can only read up to 4 at once. 223 * 224 * We're lucky in this case, because executing the RDID instruction twice will 225 * result in the same result. 226 * 227 * What we do is as follows (C: write command/opcode byte, D: read data byte, 228 * A: write address byte): 229 * 230 * 1. C D D D 231 * 2. C A A A D D D 232 */ 233static bool wpcm_fiu_rdid_match(const struct spi_mem_op *op) 234{ 235 return op->cmd.opcode == 0x9f && op->addr.nbytes == 0 && 236 op->dummy.nbytes == 0 && op->data.nbytes == 6 && 237 op->data.dir == SPI_MEM_DATA_IN; 238} 239 240static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op) 241{ 242 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); 243 int cs = spi_get_chipselect(mem->spi, 0); 244 245 /* First transfer */ 246 wpcm_fiu_set_opcode(fiu, op->cmd.opcode); 247 wpcm_fiu_set_addr(fiu, 0); 248 wpcm_fiu_do_uma(fiu, cs, false, false, 3); 249 wpcm_fiu_get_data(fiu, op->data.buf.in, 3); 250 251 /* Second transfer */ 252 wpcm_fiu_set_opcode(fiu, op->cmd.opcode); 253 wpcm_fiu_set_addr(fiu, 0); 254 wpcm_fiu_do_uma(fiu, cs, true, false, 3); 255 wpcm_fiu_get_data(fiu, op->data.buf.in + 3, 3); 256 257 return 0; 258} 259 260/* 261 * With some dummy bytes. 262 * 263 * C A A A X* X D D D D 264 * [C A A A D*][C D D D D] 265 */ 266static bool wpcm_fiu_dummy_match(const struct spi_mem_op *op) 267{ 268 // Opcode 0x0b (FAST READ) is treated differently in hardware 269 if (op->cmd.opcode == 0x0b) 270 return false; 271 272 return (op->addr.nbytes == 0 || op->addr.nbytes == 3) && 273 op->dummy.nbytes >= 1 && op->dummy.nbytes <= 5 && 274 op->data.nbytes <= 4; 275} 276 277static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op) 278{ 279 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); 280 int cs = spi_get_chipselect(mem->spi, 0); 281 282 wpcm_fiu_ects_assert(fiu, cs); 283 284 /* First transfer */ 285 wpcm_fiu_set_opcode(fiu, op->cmd.opcode); 286 wpcm_fiu_set_addr(fiu, op->addr.val); 287 wpcm_fiu_do_uma(fiu, cs, op->addr.nbytes != 0, true, op->dummy.nbytes - 1); 288 289 /* Second transfer */ 290 wpcm_fiu_set_opcode(fiu, 0); 291 wpcm_fiu_set_addr(fiu, 0); 292 wpcm_fiu_do_uma(fiu, cs, false, false, op->data.nbytes); 293 wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); 294 295 wpcm_fiu_ects_deassert(fiu, cs); 296 297 return 0; 298} 299 300static const struct wpcm_fiu_op_shape wpcm_fiu_op_shapes[] = { 301 { .match = wpcm_fiu_normal_match, .exec = wpcm_fiu_normal_exec }, 302 { .match = wpcm_fiu_fast_read_match, .exec = wpcm_fiu_fast_read_exec }, 303 { .match = wpcm_fiu_4ba_match, .exec = wpcm_fiu_4ba_exec }, 304 { .match = wpcm_fiu_rdid_match, .exec = wpcm_fiu_rdid_exec }, 305 { .match = wpcm_fiu_dummy_match, .exec = wpcm_fiu_dummy_exec }, 306}; 307 308static const struct wpcm_fiu_op_shape *wpcm_fiu_find_op_shape(const struct spi_mem_op *op) 309{ 310 size_t i; 311 312 for (i = 0; i < ARRAY_SIZE(wpcm_fiu_op_shapes); i++) { 313 const struct wpcm_fiu_op_shape *shape = &wpcm_fiu_op_shapes[i]; 314 315 if (shape->match(op)) 316 return shape; 317 } 318 319 return NULL; 320} 321 322static bool wpcm_fiu_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) 323{ 324 if (!spi_mem_default_supports_op(mem, op)) 325 return false; 326 327 if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) 328 return false; 329 330 if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 || 331 op->dummy.buswidth > 1 || op->data.buswidth > 1) 332 return false; 333 334 return wpcm_fiu_find_op_shape(op) != NULL; 335} 336 337/* 338 * In order to ensure the integrity of SPI transfers performed via UMA, 339 * temporarily disable (stall) memory accesses coming from the host CPU. 340 */ 341static void wpcm_fiu_stall_host(struct wpcm_fiu_spi *fiu, bool stall) 342{ 343 if (fiu->shm_regmap) { 344 int res = regmap_update_bits(fiu->shm_regmap, SHM_FLASH_SIZE, 345 SHM_FLASH_SIZE_STALL_HOST, 346 stall ? SHM_FLASH_SIZE_STALL_HOST : 0); 347 if (res) 348 dev_warn(fiu->dev, "Failed to (un)stall host memory accesses: %d\n", res); 349 } 350} 351 352static int wpcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 353{ 354 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); 355 const struct wpcm_fiu_op_shape *shape = wpcm_fiu_find_op_shape(op); 356 357 wpcm_fiu_stall_host(fiu, true); 358 359 if (shape) 360 return shape->exec(mem, op); 361 362 wpcm_fiu_stall_host(fiu, false); 363 364 return -EOPNOTSUPP; 365} 366 367static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 368{ 369 if (op->data.nbytes > 4) 370 op->data.nbytes = 4; 371 372 return 0; 373} 374 375static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) 376{ 377 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); 378 int cs = spi_get_chipselect(desc->mem->spi, 0); 379 380 if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) 381 return -ENOTSUPP; 382 383 /* 384 * Unfortunately, FIU only supports a 16 MiB direct mapping window (per 385 * attached flash chip), but the SPI MEM core doesn't support partial 386 * direct mappings. This means that we can't support direct mapping on 387 * flashes that are bigger than 16 MiB. 388 */ 389 if (desc->info.offset + desc->info.length > MAX_MEMORY_SIZE_PER_CS) 390 return -ENOTSUPP; 391 392 /* Don't read past the memory window */ 393 if (cs * MAX_MEMORY_SIZE_PER_CS + desc->info.offset + desc->info.length > fiu->memory_size) 394 return -ENOTSUPP; 395 396 return 0; 397} 398 399static ssize_t wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) 400{ 401 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); 402 int cs = spi_get_chipselect(desc->mem->spi, 0); 403 404 if (offs >= MAX_MEMORY_SIZE_PER_CS) 405 return -ENOTSUPP; 406 407 offs += cs * MAX_MEMORY_SIZE_PER_CS; 408 409 if (!fiu->memory || offs >= fiu->memory_size) 410 return -ENOTSUPP; 411 412 len = min_t(size_t, len, fiu->memory_size - offs); 413 memcpy_fromio(buf, fiu->memory + offs, len); 414 415 return len; 416} 417 418static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = { 419 .adjust_op_size = wpcm_fiu_adjust_op_size, 420 .supports_op = wpcm_fiu_supports_op, 421 .exec_op = wpcm_fiu_exec_op, 422 .dirmap_create = wpcm_fiu_dirmap_create, 423 .dirmap_read = wpcm_fiu_direct_read, 424}; 425 426static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu) 427{ 428 /* Configure memory-mapped flash access */ 429 writeb(FIU_BURST_CFG_R16, fiu->regs + FIU_BURST_BFG); 430 writeb(MAX_MEMORY_SIZE_TOTAL / (512 << 10), fiu->regs + FIU_CFG); 431 writeb(MAX_MEMORY_SIZE_PER_CS / (512 << 10) | BIT(6), fiu->regs + FIU_SPI_FL_CFG); 432 433 /* Deassert all manually asserted chip selects */ 434 writeb(0x0f, fiu->regs + FIU_UMA_ECTS); 435} 436 437static int wpcm_fiu_probe(struct platform_device *pdev) 438{ 439 struct device *dev = &pdev->dev; 440 struct spi_controller *ctrl; 441 struct wpcm_fiu_spi *fiu; 442 struct resource *res; 443 444 ctrl = devm_spi_alloc_host(dev, sizeof(*fiu)); 445 if (!ctrl) 446 return -ENOMEM; 447 448 fiu = spi_controller_get_devdata(ctrl); 449 fiu->dev = dev; 450 451 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); 452 fiu->regs = devm_ioremap_resource(dev, res); 453 if (IS_ERR(fiu->regs)) { 454 dev_err(dev, "Failed to map registers\n"); 455 return PTR_ERR(fiu->regs); 456 } 457 458 fiu->clk = devm_clk_get_enabled(dev, NULL); 459 if (IS_ERR(fiu->clk)) 460 return PTR_ERR(fiu->clk); 461 462 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory"); 463 fiu->memory = devm_ioremap_resource(dev, res); 464 fiu->memory_size = min_t(size_t, resource_size(res), MAX_MEMORY_SIZE_TOTAL); 465 if (IS_ERR(fiu->memory)) { 466 dev_err(dev, "Failed to map flash memory window\n"); 467 return PTR_ERR(fiu->memory); 468 } 469 470 fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm"); 471 472 wpcm_fiu_hw_init(fiu); 473 474 ctrl->bus_num = -1; 475 ctrl->mem_ops = &wpcm_fiu_mem_ops; 476 ctrl->num_chipselect = 4; 477 ctrl->dev.of_node = dev->of_node; 478 479 /* 480 * The FIU doesn't include a clock divider, the clock is entirely 481 * determined by the AHB3 bus clock. 482 */ 483 ctrl->min_speed_hz = clk_get_rate(fiu->clk); 484 ctrl->max_speed_hz = clk_get_rate(fiu->clk); 485 486 return devm_spi_register_controller(dev, ctrl); 487} 488 489static const struct of_device_id wpcm_fiu_dt_ids[] = { 490 { .compatible = "nuvoton,wpcm450-fiu", }, 491 { } 492}; 493MODULE_DEVICE_TABLE(of, wpcm_fiu_dt_ids); 494 495static struct platform_driver wpcm_fiu_driver = { 496 .driver = { 497 .name = "wpcm450-fiu", 498 .bus = &platform_bus_type, 499 .of_match_table = wpcm_fiu_dt_ids, 500 }, 501 .probe = wpcm_fiu_probe, 502}; 503module_platform_driver(wpcm_fiu_driver); 504 505MODULE_DESCRIPTION("Nuvoton WPCM450 FIU SPI controller driver"); 506MODULE_AUTHOR("Jonathan Neusch��fer <j.neuschaefer@gmx.net>"); 507MODULE_LICENSE("GPL"); 508