Searched refs:clr (Results 126 - 150 of 230) sorted by relevance

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/linux-master/drivers/net/can/
H A Dbxcan.c631 u32 clr, set; local
715 clr = BXCAN_IER_WKUIE | BXCAN_IER_SLKIE | BXCAN_IER_FOVIE1 |
724 clr |= BXCAN_IER_LECIE;
726 bxcan_rmw(priv, &regs->ier, clr, set);
/linux-master/arch/sparc/lib/
H A Dchecksum_64.S46 clr %o4
H A Dcopy_user.S278 clr %o0
368 clr %o0
/linux-master/arch/arm/include/asm/
H A Darm_pmuv3.h196 static inline void kvm_clr_pmu_events(u32 clr) {} argument
/linux-master/drivers/soc/fsl/qe/
H A Dtsa.c153 static inline void tsa_clrbits32(void __iomem *addr, u32 clr) argument
155 tsa_write32(addr, tsa_read32(addr) & ~clr);
158 static inline void tsa_clrsetbits32(void __iomem *addr, u32 clr, u32 set) argument
160 tsa_write32(addr, (tsa_read32(addr) & ~clr) | set);
/linux-master/drivers/net/wan/framer/pef2256/
H A Dpef2256.c67 static void pef2256_clrbits8(struct pef2256 *pef2256, int offset, u8 clr) argument
69 regmap_clear_bits(pef2256->regmap, offset, clr);
77 static void pef2256_clrsetbits8(struct pef2256 *pef2256, int offset, u8 clr, u8 set) argument
79 regmap_update_bits(pef2256->regmap, offset, clr | set, set);
/linux-master/drivers/net/wireless/ath/
H A Dath.h133 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
/linux-master/drivers/phy/xilinx/
H A Dphy-zynqmp.c266 u32 clr, u32 set)
270 value &= ~clr;
293 u32 reg, u32 clr, u32 set)
298 writel((readl(addr) & ~clr) | set, addr);
265 xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg, u32 clr, u32 set) argument
292 xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy, u32 reg, u32 clr, u32 set) argument
/linux-master/drivers/counter/
H A Dstm32-timer-cnt.c615 u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */ local
635 clr &= ~TIM_SR_UIF;
642 clr &= ~TIM_SR_CC_IF(i);
647 regmap_write(priv->regmap, TIM_SR, clr);
/linux-master/drivers/net/wireless/ath/ath9k/
H A Dinit.c216 u32 set, u32 clr)
221 val &= ~clr;
228 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument
238 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
241 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
215 __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, u32 set, u32 clr) argument
/linux-master/arch/arm64/kvm/
H A Darch_timer.c767 u64 clr, set; local
817 clr = 0;
819 assign_clear_set_bit(tpt, CNTHCTL_EL1PCEN << 10, set, clr);
820 assign_clear_set_bit(tpc, CNTHCTL_EL1PCTEN << 10, set, clr);
823 sysreg_clear_set(cnthctl_el2, clr, set);
/linux-master/sound/soc/rockchip/
H A Drockchip_i2s_tdm.c212 unsigned int clr)
218 bool tx = clr & I2S_CLR_TXC;
219 bool rx = clr & I2S_CLR_RXC;
235 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
211 rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm, unsigned int clr) argument
/linux-master/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c470 u32 old, new, clr = 0, set = 0; local
477 clr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
484 clr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
486 clr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
515 new = (old & ~clr) | set;
/linux-master/drivers/spi/
H A Dspi-s3c64xx.c1082 unsigned int val, clr = 0; local
1087 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1091 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1095 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1099 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1112 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
H A Dspi-pic32-sqi.c160 static inline void pic32_clrbits(void __iomem *reg, u32 clr) argument
162 writel(readl(reg) & ~clr, reg);
/linux-master/drivers/media/pci/intel/ipu3/
H A Dipu3-cio2.c695 u32 clr = 0; local
700 clr |= CIO2_INT_IOC(d);
703 int_status &= ~clr;
708 u32 clr = 0; local
713 clr |= CIO2_INT_IOS_IOLN(d);
718 int_status &= ~clr;
/linux-master/arch/m68k/fpsp040/
H A Dget_op.S539 fmovel #0,%FPSR |clr fpsr from decbin
576 bge finish |if clr, go on
H A Dround.S158 bras end_sd |if words 3 and 4 are clr, exit
432 beq no_inex |if clr, no inex
449 beqs no_inex |if clr, no inex
462 beqs no_inex |if clr, no inex
/linux-master/arch/m68k/ifpsp060/
H A Diskeleton.S214 clr.l %d0
265 clr.l %d0
/linux-master/drivers/net/phy/
H A Dmicrochip_t1.c203 u8 offset, u16 mask, u16 clr)
207 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,
202 access_smi_poll_timeout(struct phy_device *phydev, u8 offset, u16 mask, u16 clr) argument
/linux-master/drivers/gpu/drm/xe/
H A Dxe_hwmon.c126 u32 clr, u32 set, int channel)
140 *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
124 xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, enum xe_hwmon_reg_operation operation, u64 *value, u32 clr, u32 set, int channel) argument
H A Dxe_mmio.c463 u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set) argument
468 reg_val = (old & ~clr) | set;
/linux-master/arch/sparc/kernel/
H A Dwof.S263 clr %l6
/linux-master/arch/sparc/mm/
H A Dswift.S76 clr %o0
/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.c47 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr) argument
52 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
63 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set) argument
67 rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;

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