1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PEF2256 also known as FALC56 driver 4 * 5 * Copyright 2023 CS GROUP France 6 * 7 * Author: Herve Codina <herve.codina@bootlin.com> 8 */ 9 10#include <linux/framer/pef2256.h> 11#include <linux/clk.h> 12#include <linux/framer/framer-provider.h> 13#include <linux/gpio/consumer.h> 14#include <linux/interrupt.h> 15#include <linux/io.h> 16#include <linux/mfd/core.h> 17#include <linux/module.h> 18#include <linux/notifier.h> 19#include <linux/of.h> 20#include <linux/of_platform.h> 21#include <linux/platform_device.h> 22#include <linux/regmap.h> 23#include <linux/slab.h> 24#include "pef2256-regs.h" 25 26enum pef2256_frame_type { 27 PEF2256_FRAME_E1_DOUBLEFRAME, 28 PEF2256_FRAME_E1_CRC4_MULTIFRAME, 29 PEF2256_FRAME_E1_AUTO_MULTIFRAME, 30 PEF2256_FRAME_T1J1_4FRAME, 31 PEF2256_FRAME_T1J1_12FRAME, 32 PEF2256_FRAME_T1J1_24FRAME, 33 PEF2256_FRAME_T1J1_72FRAME, 34}; 35 36struct pef2256 { 37 struct device *dev; 38 struct regmap *regmap; 39 enum pef2256_version version; 40 struct clk *mclk; 41 struct clk *sclkr; 42 struct clk *sclkx; 43 struct gpio_desc *reset_gpio; 44 unsigned long sysclk_rate; 45 u32 data_rate; 46 bool is_tx_falling_edge; 47 bool is_subordinate; 48 enum pef2256_frame_type frame_type; 49 u8 channel_phase; 50 atomic_t carrier; 51 struct framer *framer; 52}; 53 54static u8 pef2256_read8(struct pef2256 *pef2256, int offset) 55{ 56 int val; 57 58 regmap_read(pef2256->regmap, offset, &val); 59 return val; 60} 61 62static void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val) 63{ 64 regmap_write(pef2256->regmap, offset, val); 65} 66 67static void pef2256_clrbits8(struct pef2256 *pef2256, int offset, u8 clr) 68{ 69 regmap_clear_bits(pef2256->regmap, offset, clr); 70} 71 72static void pef2256_setbits8(struct pef2256 *pef2256, int offset, u8 set) 73{ 74 regmap_set_bits(pef2256->regmap, offset, set); 75} 76 77static void pef2256_clrsetbits8(struct pef2256 *pef2256, int offset, u8 clr, u8 set) 78{ 79 regmap_update_bits(pef2256->regmap, offset, clr | set, set); 80} 81 82enum pef2256_version pef2256_get_version(struct pef2256 *pef2256) 83{ 84 enum pef2256_version version = PEF2256_VERSION_UNKNOWN; 85 u8 vstr, wid; 86 87 vstr = pef2256_read8(pef2256, PEF2256_VSTR); 88 wid = pef2256_read8(pef2256, PEF2256_WID); 89 90 switch (vstr) { 91 case PEF2256_VSTR_VERSION_12: 92 if ((wid & PEF2256_12_WID_MASK) == PEF2256_12_WID_VERSION_12) 93 version = PEF2256_VERSION_1_2; 94 break; 95 case PEF2256_VSTR_VERSION_2x: 96 switch (wid & PEF2256_2X_WID_MASK) { 97 case PEF2256_2X_WID_VERSION_21: 98 version = PEF2256_VERSION_2_1; 99 break; 100 case PEF2256_2X_WID_VERSION_22: 101 version = PEF2256_VERSION_2_2; 102 break; 103 } 104 break; 105 case PEF2256_VSTR_VERSION_21: 106 version = PEF2256_VERSION_2_1; 107 break; 108 } 109 110 if (version == PEF2256_VERSION_UNKNOWN) 111 dev_err(pef2256->dev, "Unknown version (0x%02x, 0x%02x)\n", vstr, wid); 112 113 return version; 114} 115EXPORT_SYMBOL_GPL(pef2256_get_version); 116 117enum pef2256_gcm_config_item { 118 PEF2256_GCM_CONFIG_1544000 = 0, 119 PEF2256_GCM_CONFIG_2048000, 120 PEF2256_GCM_CONFIG_8192000, 121 PEF2256_GCM_CONFIG_10000000, 122 PEF2256_GCM_CONFIG_12352000, 123 PEF2256_GCM_CONFIG_16384000, 124}; 125 126struct pef2256_gcm_config { 127 u8 gcm_12[6]; 128 u8 gcm_2x[8]; 129}; 130 131static const struct pef2256_gcm_config pef2256_gcm_configs[] = { 132 [PEF2256_GCM_CONFIG_1544000] = { 133 .gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x00, 0x15}, 134 .gcm_2x = {0x00, 0x15, 0x00, 0x08, 0x00, 0x3F, 0x9C, 0xDF}, 135 }, 136 [PEF2256_GCM_CONFIG_2048000] = { 137 .gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x00, 0x10}, 138 .gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x2F, 0xDB, 0xDF}, 139 }, 140 [PEF2256_GCM_CONFIG_8192000] = { 141 .gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x03, 0x10}, 142 .gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x0B, 0xDB, 0xDF}, 143 }, 144 [PEF2256_GCM_CONFIG_10000000] = { 145 .gcm_12 = {0x90, 0x51, 0x81, 0x8F, 0x04, 0x10}, 146 .gcm_2x = {0x40, 0x1B, 0x3D, 0x0A, 0x00, 0x07, 0xC9, 0xDC}, 147 }, 148 [PEF2256_GCM_CONFIG_12352000] = { 149 .gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x07, 0x15}, 150 .gcm_2x = {0x00, 0x19, 0x00, 0x08, 0x01, 0x0A, 0x98, 0xDA}, 151 }, 152 [PEF2256_GCM_CONFIG_16384000] = { 153 .gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x07, 0x10}, 154 .gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x01, 0x0B, 0xDB, 0xDF}, 155 }, 156}; 157 158static int pef2256_setup_gcm(struct pef2256 *pef2256) 159{ 160 enum pef2256_gcm_config_item item; 161 unsigned long mclk_rate; 162 const u8 *gcm; 163 int i, count; 164 165 mclk_rate = clk_get_rate(pef2256->mclk); 166 switch (mclk_rate) { 167 case 1544000: 168 item = PEF2256_GCM_CONFIG_1544000; 169 break; 170 case 2048000: 171 item = PEF2256_GCM_CONFIG_2048000; 172 break; 173 case 8192000: 174 item = PEF2256_GCM_CONFIG_8192000; 175 break; 176 case 10000000: 177 item = PEF2256_GCM_CONFIG_10000000; 178 break; 179 case 12352000: 180 item = PEF2256_GCM_CONFIG_12352000; 181 break; 182 case 16384000: 183 item = PEF2256_GCM_CONFIG_16384000; 184 break; 185 default: 186 dev_err(pef2256->dev, "Unsupported v2.x MCLK rate %lu\n", mclk_rate); 187 return -EINVAL; 188 } 189 190 BUILD_BUG_ON(item >= ARRAY_SIZE(pef2256_gcm_configs)); 191 192 if (pef2256->version == PEF2256_VERSION_1_2) { 193 gcm = pef2256_gcm_configs[item].gcm_12; 194 count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_12); 195 } else { 196 gcm = pef2256_gcm_configs[item].gcm_2x; 197 count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_2x); 198 } 199 200 for (i = 0; i < count; i++) 201 pef2256_write8(pef2256, PEF2256_GCM(i + 1), *(gcm + i)); 202 203 return 0; 204} 205 206static int pef2256_setup_e1_line(struct pef2256 *pef2256) 207{ 208 u8 fmr1, fmr2; 209 210 /* RCLK output : DPLL clock, DCO-X enabled, DCO-X internal ref clock */ 211 pef2256_write8(pef2256, PEF2256_CMR1, 0x00); 212 213 /* SCLKR selected, SCLKX selected, 214 * receive synchro pulse sourced by SYPR, 215 * transmit synchro pulse sourced by SYPX, 216 * DCO-X center frequency enabled 217 */ 218 pef2256_write8(pef2256, PEF2256_CMR2, PEF2256_CMR2_DCOXC); 219 220 if (pef2256->is_subordinate) { 221 /* select RCLK source = 2M, disable switching from RCLK to SYNC */ 222 pef2256_clrsetbits8(pef2256, PEF2256_CMR1, PEF2256_CMR1_RS_MASK, 223 PEF2256_CMR1_RS_DCOR_2048 | PEF2256_CMR1_DCS); 224 } 225 226 /* slave mode, local loop off, mode short-haul 227 * In v2.x, bit3 is a forced 1 bit in the datasheet -> Need to be set. 228 */ 229 if (pef2256->version == PEF2256_VERSION_1_2) 230 pef2256_write8(pef2256, PEF2256_LIM0, 0x00); 231 else 232 pef2256_write8(pef2256, PEF2256_LIM0, PEF2256_2X_LIM0_BIT3); 233 234 /* "master" mode */ 235 if (!pef2256->is_subordinate) 236 pef2256_setbits8(pef2256, PEF2256_LIM0, PEF2256_LIM0_MAS); 237 238 /* analog interface selected, remote loop off */ 239 pef2256_write8(pef2256, PEF2256_LIM1, 0x00); 240 241 /* receive input threshold = 0,21V */ 242 if (pef2256->version == PEF2256_VERSION_1_2) 243 pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_12_LIM1_RIL_MASK, 244 PEF2256_12_LIM1_RIL_210); 245 else 246 pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_2X_LIM1_RIL_MASK, 247 PEF2256_2X_LIM1_RIL_210); 248 249 /* transmit pulse mask, default value from datasheet 250 * transmit line in normal operation 251 */ 252 if (pef2256->version == PEF2256_VERSION_1_2) 253 pef2256_write8(pef2256, PEF2256_XPM0, 0x7B); 254 else 255 pef2256_write8(pef2256, PEF2256_XPM0, 0x9C); 256 pef2256_write8(pef2256, PEF2256_XPM1, 0x03); 257 pef2256_write8(pef2256, PEF2256_XPM2, 0x00); 258 259 /* HDB3 coding, no alarm simulation */ 260 pef2256_write8(pef2256, PEF2256_FMR0, PEF2256_FMR0_XC_HDB3 | PEF2256_FMR0_RC_HDB3); 261 262 /* E1, frame format, 2 Mbit/s system data rate, no AIS 263 * transmission to remote end or system interface, payload loop 264 * off, transmit remote alarm on 265 */ 266 fmr1 = 0x00; 267 fmr2 = PEF2256_FMR2_AXRA; 268 switch (pef2256->frame_type) { 269 case PEF2256_FRAME_E1_DOUBLEFRAME: 270 fmr2 |= PEF2256_FMR2_RFS_DOUBLEFRAME; 271 break; 272 case PEF2256_FRAME_E1_CRC4_MULTIFRAME: 273 fmr1 |= PEF2256_FMR1_XFS; 274 fmr2 |= PEF2256_FMR2_RFS_CRC4_MULTIFRAME; 275 break; 276 case PEF2256_FRAME_E1_AUTO_MULTIFRAME: 277 fmr1 |= PEF2256_FMR1_XFS; 278 fmr2 |= PEF2256_FMR2_RFS_AUTO_MULTIFRAME; 279 break; 280 default: 281 dev_err(pef2256->dev, "Unsupported frame type %d\n", pef2256->frame_type); 282 return -EINVAL; 283 } 284 pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_XFS, fmr1); 285 pef2256_write8(pef2256, PEF2256_FMR2, fmr2); 286 287 if (!pef2256->is_subordinate) { 288 /* SEC input, active high */ 289 pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_SEC_IN_HIGH); 290 } else { 291 /* FSC output, active high */ 292 pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_FSC_OUT_HIGH); 293 } 294 295 /* SCLKR, SCLKX, RCLK configured to inputs, 296 * XFMS active low, CLK1 and CLK2 pin configuration 297 */ 298 pef2256_write8(pef2256, PEF2256_PC5, 0x00); 299 pef2256_write8(pef2256, PEF2256_PC6, 0x00); 300 301 /* port RCLK is output */ 302 pef2256_setbits8(pef2256, PEF2256_PC5, PEF2256_PC5_CRP); 303 304 return 0; 305} 306 307static void pef2256_setup_e1_los(struct pef2256 *pef2256) 308{ 309 /* detection of LOS alarm = 176 pulses (ie (10 + 1) * 16) */ 310 pef2256_write8(pef2256, PEF2256_PCD, 10); 311 /* recovery of LOS alarm = 22 pulses (ie 21 + 1) */ 312 pef2256_write8(pef2256, PEF2256_PCR, 21); 313 /* E1 default for the receive slicer threshold */ 314 pef2256_write8(pef2256, PEF2256_LIM2, PEF2256_LIM2_SLT_THR50); 315 if (pef2256->is_subordinate) { 316 /* Loop-timed */ 317 pef2256_setbits8(pef2256, PEF2256_LIM2, PEF2256_LIM2_ELT); 318 } 319} 320 321static int pef2256_setup_e1_system(struct pef2256 *pef2256) 322{ 323 u8 sic1, fmr1; 324 325 /* 2.048 MHz system clocking rate, receive buffer 2 frames, transmit 326 * buffer bypass, data sampled and transmitted on the falling edge of 327 * SCLKR/X, automatic freeze signaling, data is active in the first 328 * channel phase 329 */ 330 pef2256_write8(pef2256, PEF2256_SIC1, 0x00); 331 pef2256_write8(pef2256, PEF2256_SIC2, 0x00); 332 pef2256_write8(pef2256, PEF2256_SIC3, 0x00); 333 334 if (pef2256->is_subordinate) { 335 /* transmit buffer size = 2 frames, transparent mode */ 336 pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_XBS_MASK, 337 PEF2256_SIC1_XBS_2FRAMES); 338 } 339 340 if (pef2256->version != PEF2256_VERSION_1_2) { 341 /* during inactive channel phase switch RDO/RSIG into tri-state */ 342 pef2256_setbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RTRI); 343 } 344 345 if (pef2256->is_tx_falling_edge) { 346 /* falling edge sync pulse transmit, rising edge sync pulse receive */ 347 pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESX, PEF2256_SIC3_RESR); 348 } else { 349 /* rising edge sync pulse transmit, falling edge sync pulse receive */ 350 pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESR, PEF2256_SIC3_RESX); 351 } 352 353 /* transmit offset counter (XCO10..0) = 4 */ 354 pef2256_write8(pef2256, PEF2256_XC0, 0); 355 pef2256_write8(pef2256, PEF2256_XC1, 4); 356 /* receive offset counter (RCO10..0) = 4 */ 357 pef2256_write8(pef2256, PEF2256_RC0, 0); 358 pef2256_write8(pef2256, PEF2256_RC1, 4); 359 360 /* system clock rate */ 361 switch (pef2256->sysclk_rate) { 362 case 2048000: 363 sic1 = PEF2256_SIC1_SSC_2048; 364 break; 365 case 4096000: 366 sic1 = PEF2256_SIC1_SSC_4096; 367 break; 368 case 8192000: 369 sic1 = PEF2256_SIC1_SSC_8192; 370 break; 371 case 16384000: 372 sic1 = PEF2256_SIC1_SSC_16384; 373 break; 374 default: 375 dev_err(pef2256->dev, "Unsupported sysclk rate %lu\n", pef2256->sysclk_rate); 376 return -EINVAL; 377 } 378 pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSC_MASK, sic1); 379 380 /* data clock rate */ 381 switch (pef2256->data_rate) { 382 case 2048000: 383 fmr1 = PEF2256_FMR1_SSD_2048; 384 sic1 = PEF2256_SIC1_SSD_2048; 385 break; 386 case 4096000: 387 fmr1 = PEF2256_FMR1_SSD_4096; 388 sic1 = PEF2256_SIC1_SSD_4096; 389 break; 390 case 8192000: 391 fmr1 = PEF2256_FMR1_SSD_8192; 392 sic1 = PEF2256_SIC1_SSD_8192; 393 break; 394 case 16384000: 395 fmr1 = PEF2256_FMR1_SSD_16384; 396 sic1 = PEF2256_SIC1_SSD_16384; 397 break; 398 default: 399 dev_err(pef2256->dev, "Unsupported data rate %u\n", pef2256->data_rate); 400 return -EINVAL; 401 } 402 pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_SSD_MASK, fmr1); 403 pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSD_MASK, sic1); 404 405 /* channel phase */ 406 pef2256_clrsetbits8(pef2256, PEF2256_SIC2, PEF2256_SIC2_SICS_MASK, 407 PEF2256_SIC2_SICS(pef2256->channel_phase)); 408 409 return 0; 410} 411 412static void pef2256_setup_e1_signaling(struct pef2256 *pef2256) 413{ 414 /* All bits of the transmitted service word are cleared */ 415 pef2256_write8(pef2256, PEF2256_XSW, PEF2256_XSW_XY(0x1F)); 416 417 /* CAS disabled and clear spare bit values */ 418 pef2256_write8(pef2256, PEF2256_XSP, 0x00); 419 420 if (pef2256->is_subordinate) { 421 /* transparent mode */ 422 pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XTM); 423 } 424 425 /* Si-Bit, Spare bit For International, FAS word */ 426 pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XSIS); 427 pef2256_setbits8(pef2256, PEF2256_XSP, PEF2256_XSP_XSIF); 428 429 /* no transparent mode active */ 430 pef2256_write8(pef2256, PEF2256_TSWM, 0x00); 431} 432 433static void pef2256_setup_e1_errors(struct pef2256 *pef2256) 434{ 435 /* error counter latched every 1s */ 436 pef2256_setbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_ECM); 437 438 /* error counter mode COFA */ 439 pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_ECMC); 440 441 /* errors in service words have no influence */ 442 pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_SWD); 443 444 /* 4 consecutive incorrect FAS causes loss of sync */ 445 pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_ASY4); 446} 447 448static int pef2256_setup_e1(struct pef2256 *pef2256) 449{ 450 int ret; 451 452 /* Setup, Master clocking mode (GCM8..1) */ 453 ret = pef2256_setup_gcm(pef2256); 454 if (ret) 455 return ret; 456 457 /* Select E1 mode */ 458 pef2256_write8(pef2256, PEF2256_FMR1, 0x00); 459 460 /* internal second timer, power on */ 461 pef2256_write8(pef2256, PEF2256_GCR, 0x00); 462 463 /* Setup line interface */ 464 ret = pef2256_setup_e1_line(pef2256); 465 if (ret) 466 return ret; 467 468 /* Setup Loss-of-signal detection and recovery */ 469 pef2256_setup_e1_los(pef2256); 470 471 /* Setup system interface */ 472 ret = pef2256_setup_e1_system(pef2256); 473 if (ret) 474 return ret; 475 476 /* Setup signaling */ 477 pef2256_setup_e1_signaling(pef2256); 478 479 /* Setup errors counters and condition */ 480 pef2256_setup_e1_errors(pef2256); 481 482 /* status changed interrupt at both up and down */ 483 pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_SCI); 484 485 /* Clear any ISR2 pending interrupts and unmask needed interrupts */ 486 pef2256_read8(pef2256, PEF2256_ISR2); 487 pef2256_clrbits8(pef2256, PEF2256_IMR2, PEF2256_INT2_LOS | PEF2256_INT2_AIS); 488 489 /* reset lines */ 490 pef2256_write8(pef2256, PEF2256_CMDR, PEF2256_CMDR_RRES | PEF2256_CMDR_XRES); 491 return 0; 492} 493 494static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr) 495{ 496 dev_warn_ratelimited(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr); 497} 498 499static bool pef2256_is_carrier_on(struct pef2256 *pef2256) 500{ 501 u8 frs0; 502 503 frs0 = pef2256_read8(pef2256, PEF2256_FRS0); 504 return !(frs0 & (PEF2256_FRS0_LOS | PEF2256_FRS0_AIS)); 505} 506 507static void pef2256_isr2_handler(struct pef2256 *pef2256, u8 nbr, u8 isr) 508{ 509 bool carrier; 510 511 if (isr & (PEF2256_INT2_LOS | PEF2256_INT2_AIS)) { 512 carrier = pef2256_is_carrier_on(pef2256); 513 if (atomic_xchg(&pef2256->carrier, carrier) != carrier) 514 framer_notify_status_change(pef2256->framer); 515 } 516} 517 518static irqreturn_t pef2256_irq_handler(int irq, void *priv) 519{ 520 static void (*pef2256_isr_handler[])(struct pef2256 *, u8, u8) = { 521 [0] = pef2256_isr_default_handler, 522 [1] = pef2256_isr_default_handler, 523 [2] = pef2256_isr2_handler, 524 [3] = pef2256_isr_default_handler, 525 [4] = pef2256_isr_default_handler, 526 [5] = pef2256_isr_default_handler 527 }; 528 struct pef2256 *pef2256 = (struct pef2256 *)priv; 529 u8 gis; 530 u8 isr; 531 u8 n; 532 533 gis = pef2256_read8(pef2256, PEF2256_GIS); 534 535 for (n = 0; n < ARRAY_SIZE(pef2256_isr_handler); n++) { 536 if (gis & PEF2256_GIS_ISR(n)) { 537 isr = pef2256_read8(pef2256, PEF2256_ISR(n)); 538 pef2256_isr_handler[n](pef2256, n, isr); 539 } 540 } 541 542 return IRQ_HANDLED; 543} 544 545static int pef2256_check_rates(struct pef2256 *pef2256, unsigned long sysclk_rate, 546 unsigned long data_rate) 547{ 548 unsigned long rate; 549 550 switch (sysclk_rate) { 551 case 2048000: 552 case 4096000: 553 case 8192000: 554 case 16384000: 555 break; 556 default: 557 dev_err(pef2256->dev, "Unsupported system clock rate %lu\n", sysclk_rate); 558 return -EINVAL; 559 } 560 561 for (rate = data_rate; rate <= data_rate * 4; rate *= 2) { 562 if (rate == sysclk_rate) 563 return 0; 564 } 565 dev_err(pef2256->dev, "Unsupported data rate %lu with system clock rate %lu\n", 566 data_rate, sysclk_rate); 567 return -EINVAL; 568} 569 570static int pef2556_of_parse(struct pef2256 *pef2256, struct device_node *np) 571{ 572 int ret; 573 574 pef2256->data_rate = 2048000; 575 ret = of_property_read_u32(np, "lantiq,data-rate-bps", &pef2256->data_rate); 576 if (ret && ret != -EINVAL) { 577 dev_err(pef2256->dev, "%pOF: failed to read lantiq,data-rate-bps\n", np); 578 return ret; 579 } 580 581 ret = pef2256_check_rates(pef2256, pef2256->sysclk_rate, pef2256->data_rate); 582 if (ret) 583 return ret; 584 585 pef2256->is_tx_falling_edge = of_property_read_bool(np, "lantiq,clock-falling-edge"); 586 587 pef2256->channel_phase = 0; 588 ret = of_property_read_u8(np, "lantiq,channel-phase", &pef2256->channel_phase); 589 if (ret && ret != -EINVAL) { 590 dev_err(pef2256->dev, "%pOF: failed to read lantiq,channel-phase\n", 591 np); 592 return ret; 593 } 594 if (pef2256->channel_phase >= pef2256->sysclk_rate / pef2256->data_rate) { 595 dev_err(pef2256->dev, "%pOF: Invalid lantiq,channel-phase %u\n", 596 np, pef2256->channel_phase); 597 return -EINVAL; 598 } 599 600 return 0; 601} 602 603static const struct regmap_config pef2256_regmap_config = { 604 .reg_bits = 32, 605 .val_bits = 8, 606 .max_register = 0xff, 607}; 608 609static const struct mfd_cell pef2256_devs[] = { 610 { .name = "lantiq-pef2256-pinctrl", }, 611}; 612 613static int pef2256_add_audio_devices(struct pef2256 *pef2256) 614{ 615 const char *compatible = "lantiq,pef2256-codec"; 616 struct mfd_cell *audio_devs; 617 struct device_node *np; 618 unsigned int count = 0; 619 unsigned int i; 620 int ret; 621 622 for_each_available_child_of_node(pef2256->dev->of_node, np) { 623 if (of_device_is_compatible(np, compatible)) 624 count++; 625 } 626 627 if (!count) 628 return 0; 629 630 audio_devs = kcalloc(count, sizeof(*audio_devs), GFP_KERNEL); 631 if (!audio_devs) 632 return -ENOMEM; 633 634 for (i = 0; i < count; i++) { 635 audio_devs[i].name = "framer-codec"; 636 audio_devs[i].of_compatible = compatible; 637 audio_devs[i].id = i; 638 } 639 640 ret = mfd_add_devices(pef2256->dev, 0, audio_devs, count, NULL, 0, NULL); 641 kfree(audio_devs); 642 return ret; 643} 644 645static int pef2256_framer_get_status(struct framer *framer, struct framer_status *status) 646{ 647 struct pef2256 *pef2256 = framer_get_drvdata(framer); 648 649 status->link_is_on = !!atomic_read(&pef2256->carrier); 650 return 0; 651} 652 653static int pef2256_framer_set_config(struct framer *framer, const struct framer_config *config) 654{ 655 struct pef2256 *pef2256 = framer_get_drvdata(framer); 656 657 if (config->iface != FRAMER_IFACE_E1) { 658 dev_err(pef2256->dev, "Only E1 line is currently supported\n"); 659 return -EOPNOTSUPP; 660 } 661 662 switch (config->clock_type) { 663 case FRAMER_CLOCK_EXT: 664 pef2256->is_subordinate = true; 665 break; 666 case FRAMER_CLOCK_INT: 667 pef2256->is_subordinate = false; 668 break; 669 default: 670 return -EINVAL; 671 } 672 673 /* Apply the new settings */ 674 return pef2256_setup_e1(pef2256); 675} 676 677static int pef2256_framer_get_config(struct framer *framer, struct framer_config *config) 678{ 679 struct pef2256 *pef2256 = framer_get_drvdata(framer); 680 681 config->iface = FRAMER_IFACE_E1; 682 config->clock_type = pef2256->is_subordinate ? FRAMER_CLOCK_EXT : FRAMER_CLOCK_INT; 683 config->line_clock_rate = 2048000; 684 return 0; 685} 686 687static const struct framer_ops pef2256_framer_ops = { 688 .owner = THIS_MODULE, 689 .get_status = pef2256_framer_get_status, 690 .get_config = pef2256_framer_get_config, 691 .set_config = pef2256_framer_set_config, 692}; 693 694static int pef2256_probe(struct platform_device *pdev) 695{ 696 struct device_node *np = pdev->dev.of_node; 697 unsigned long sclkr_rate, sclkx_rate; 698 struct framer_provider *framer_provider; 699 struct pef2256 *pef2256; 700 const char *version_txt; 701 void __iomem *iomem; 702 int ret; 703 int irq; 704 705 pef2256 = devm_kzalloc(&pdev->dev, sizeof(*pef2256), GFP_KERNEL); 706 if (!pef2256) 707 return -ENOMEM; 708 709 pef2256->dev = &pdev->dev; 710 atomic_set(&pef2256->carrier, 0); 711 712 pef2256->is_subordinate = true; 713 pef2256->frame_type = PEF2256_FRAME_E1_DOUBLEFRAME; 714 715 iomem = devm_platform_ioremap_resource(pdev, 0); 716 if (IS_ERR(iomem)) 717 return PTR_ERR(iomem); 718 719 pef2256->regmap = devm_regmap_init_mmio(&pdev->dev, iomem, 720 &pef2256_regmap_config); 721 if (IS_ERR(pef2256->regmap)) { 722 dev_err(&pdev->dev, "Failed to initialise Regmap (%ld)\n", 723 PTR_ERR(pef2256->regmap)); 724 return PTR_ERR(pef2256->regmap); 725 } 726 727 pef2256->mclk = devm_clk_get_enabled(&pdev->dev, "mclk"); 728 if (IS_ERR(pef2256->mclk)) 729 return PTR_ERR(pef2256->mclk); 730 731 pef2256->sclkr = devm_clk_get_enabled(&pdev->dev, "sclkr"); 732 if (IS_ERR(pef2256->sclkr)) 733 return PTR_ERR(pef2256->sclkr); 734 735 pef2256->sclkx = devm_clk_get_enabled(&pdev->dev, "sclkx"); 736 if (IS_ERR(pef2256->sclkx)) 737 return PTR_ERR(pef2256->sclkx); 738 739 /* Both SCLKR (receive) and SCLKX (transmit) must have the same rate, 740 * stored as sysclk_rate. 741 * The exact value will be checked at pef2256_check_rates() 742 */ 743 sclkr_rate = clk_get_rate(pef2256->sclkr); 744 sclkx_rate = clk_get_rate(pef2256->sclkx); 745 if (sclkr_rate != sclkx_rate) { 746 dev_err(pef2256->dev, "clk rate mismatch. sclkr %lu Hz, sclkx %lu Hz\n", 747 sclkr_rate, sclkx_rate); 748 return -EINVAL; 749 } 750 pef2256->sysclk_rate = sclkr_rate; 751 752 /* Reset the component. The MCLK clock must be active during reset */ 753 pef2256->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 754 if (IS_ERR(pef2256->reset_gpio)) 755 return PTR_ERR(pef2256->reset_gpio); 756 if (pef2256->reset_gpio) { 757 gpiod_set_value_cansleep(pef2256->reset_gpio, 1); 758 usleep_range(10, 20); 759 gpiod_set_value_cansleep(pef2256->reset_gpio, 0); 760 usleep_range(10, 20); 761 } 762 763 pef2256->version = pef2256_get_version(pef2256); 764 switch (pef2256->version) { 765 case PEF2256_VERSION_1_2: 766 version_txt = "1.2"; 767 break; 768 case PEF2256_VERSION_2_1: 769 version_txt = "2.1"; 770 break; 771 case PEF2256_VERSION_2_2: 772 version_txt = "2.2"; 773 break; 774 default: 775 return -ENODEV; 776 } 777 dev_info(pef2256->dev, "Version %s detected\n", version_txt); 778 779 ret = pef2556_of_parse(pef2256, np); 780 if (ret) 781 return ret; 782 783 /* Create the framer. It can be used on interrupts */ 784 pef2256->framer = devm_framer_create(pef2256->dev, NULL, &pef2256_framer_ops); 785 if (IS_ERR(pef2256->framer)) 786 return PTR_ERR(pef2256->framer); 787 788 framer_set_drvdata(pef2256->framer, pef2256); 789 790 /* Disable interrupts */ 791 pef2256_write8(pef2256, PEF2256_IMR0, 0xff); 792 pef2256_write8(pef2256, PEF2256_IMR1, 0xff); 793 pef2256_write8(pef2256, PEF2256_IMR2, 0xff); 794 pef2256_write8(pef2256, PEF2256_IMR3, 0xff); 795 pef2256_write8(pef2256, PEF2256_IMR4, 0xff); 796 pef2256_write8(pef2256, PEF2256_IMR5, 0xff); 797 798 /* Clear any pending interrupts */ 799 pef2256_read8(pef2256, PEF2256_ISR0); 800 pef2256_read8(pef2256, PEF2256_ISR1); 801 pef2256_read8(pef2256, PEF2256_ISR2); 802 pef2256_read8(pef2256, PEF2256_ISR3); 803 pef2256_read8(pef2256, PEF2256_ISR4); 804 pef2256_read8(pef2256, PEF2256_ISR5); 805 806 irq = platform_get_irq(pdev, 0); 807 if (irq < 0) 808 return irq; 809 ret = devm_request_irq(pef2256->dev, irq, pef2256_irq_handler, 0, "pef2256", pef2256); 810 if (ret < 0) 811 return ret; 812 813 platform_set_drvdata(pdev, pef2256); 814 815 ret = mfd_add_devices(pef2256->dev, 0, pef2256_devs, 816 ARRAY_SIZE(pef2256_devs), NULL, 0, NULL); 817 if (ret) { 818 dev_err(pef2256->dev, "add devices failed (%d)\n", ret); 819 return ret; 820 } 821 822 ret = pef2256_setup_e1(pef2256); 823 if (ret) 824 return ret; 825 826 framer_provider = devm_framer_provider_of_register(pef2256->dev, 827 framer_provider_simple_of_xlate); 828 if (IS_ERR(framer_provider)) 829 return PTR_ERR(framer_provider); 830 831 /* Add audio devices */ 832 ret = pef2256_add_audio_devices(pef2256); 833 if (ret < 0) { 834 dev_err(pef2256->dev, "add audio devices failed (%d)\n", ret); 835 return ret; 836 } 837 838 return 0; 839} 840 841static void pef2256_remove(struct platform_device *pdev) 842{ 843 struct pef2256 *pef2256 = platform_get_drvdata(pdev); 844 845 /* Disable interrupts */ 846 pef2256_write8(pef2256, PEF2256_IMR0, 0xff); 847 pef2256_write8(pef2256, PEF2256_IMR1, 0xff); 848 pef2256_write8(pef2256, PEF2256_IMR2, 0xff); 849 pef2256_write8(pef2256, PEF2256_IMR3, 0xff); 850 pef2256_write8(pef2256, PEF2256_IMR4, 0xff); 851 pef2256_write8(pef2256, PEF2256_IMR5, 0xff); 852} 853 854static const struct of_device_id pef2256_id_table[] = { 855 { .compatible = "lantiq,pef2256" }, 856 {} /* sentinel */ 857}; 858MODULE_DEVICE_TABLE(of, pef2256_id_table); 859 860static struct platform_driver pef2256_driver = { 861 .driver = { 862 .name = "lantiq-pef2256", 863 .of_match_table = pef2256_id_table, 864 }, 865 .probe = pef2256_probe, 866 .remove_new = pef2256_remove, 867}; 868module_platform_driver(pef2256_driver); 869 870struct regmap *pef2256_get_regmap(struct pef2256 *pef2256) 871{ 872 return pef2256->regmap; 873} 874EXPORT_SYMBOL_GPL(pef2256_get_regmap); 875 876MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>"); 877MODULE_DESCRIPTION("PEF2256 driver"); 878MODULE_LICENSE("GPL"); 879