| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 103 const TargetRegisterClass *getRegClass() const { function in class:llvm::DstOp
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveDebugVariables.cpp | 1200 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg);
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| H A D | MachineFunction.cpp | 667 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
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| H A D | ScheduleDAGInstrs.cpp | 371 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
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| H A D | LiveIntervals.cpp | 1713 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
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| H A D | TargetLoweringBase.cpp | 1144 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 749 auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 431 DefRC = TRI.getRegClass(DestReg);
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| H A D | MipsSEISelDAGToDAG.cpp | 119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
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| H A D | MipsFastISel.cpp | 1731 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 1193 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
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| H A D | AMDGPUISelDAGToDAG.cpp | 563 return MRI.getRegClass(Reg);
585 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
590 Subtarget->getRegisterInfo()->getRegClass(RCID);
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| H A D | SIISelLowering.cpp | 3481 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3545 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3603 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3677 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3818 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3831 ? MRI.getRegClass(Src0.getReg())
3834 ? MRI.getRegClass(Src1.getReg())
3915 if (TRI->getRegSizeInBits(*MRI.getRegClass(Src2.getReg())) == 64) {
4050 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyCFGStackify.cpp | 803 unsigned CopyOpc = getCopyOpcode(MRI.getRegClass(DefReg));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1245 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
1754 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
2100 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
2318 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 281 const auto *RC = TRI->getRegClass(I);
305 PerTargetMIParsingState::getRegClass(StringRef Name) { function in class:PerTargetMIParsingState
1318 const TargetRegisterClass *RC = PFS.Target.getRegClass(Name);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2366 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
2559 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
2562 TRC = TII->getRegClass(MCID, 2, TRI, *MF);
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| H A D | ARMLowOverheadLoops.cpp | 778 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID);
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| H A D | ARMFrameLowering.cpp | 1547 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 2153 SpillRCs.insert(MRI.getRegClass(VR));
2290 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2458 auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
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| H A D | HexagonConstExtenders.cpp | 1946 MRI->getRegClass(Op.getReg()) != &Hexagon::PredRegsRegClass)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1670 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
1927 static int getRegClass(RegisterKind Is, unsigned RegWidth) { function
2190 int RCID = getRegClass(RegKind, RegWidth);
2195 const MCRegisterClass RC = TRI->getRegClass(RCID);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 633 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1278 CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const { function in class:CodeGenRegBank
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 583 return *(RegInfo->getRegClass(RC).begin() + RegNo);
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