/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DwarfDebug.cpp | 656 const auto &TII = *MF->getSubtarget().getInstrInfo(); 705 if (auto ParamValue = TII.describeLoadedValue(*CurMI, ParamFwdReg)) { 856 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); 857 assert(TII && "TargetInstrInfo not found: cannot label tail calls"); 936 bool IsTail = TII->isTailCall(MI); 1935 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); 1936 bool IsTail = TII->isTailCall(*MI);
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H A D | AsmPrinter.cpp | 805 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local 812 if ((Size = MI.getRestoreSize(TII))) { 814 } else if ((Size = MI.getFoldedRestoreSize(TII))) { 817 } else if ((Size = MI.getSpillSize(TII))) { 819 } else if ((Size = MI.getFoldedSpillSize(TII))) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 133 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64)) 141 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR)) 146 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1569 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo(); local 1577 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD 1582 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); 1587 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD 1592 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); 2235 const TargetInstrInfo *TII) const { 2419 const ARMBaseInstrInfo &TII, 2422 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) 2445 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 2579 const ARMBaseInstrInfo &TII) { 2414 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument 2577 rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachinePipeliner.h | 68 const TargetInstrInfo *TII = nullptr; member in class:llvm::MachinePipeliner
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H A D | ScheduleDAG.h | 558 const TargetInstrInfo *TII; ///< Target instruction information member in class:llvm::SUnit::ScheduleDAG
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H A D | MachineRegisterInfo.h | 956 const TargetInstrInfo &TII);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | SplitKit.cpp | 162 TII(*MF.getSubtarget().getInstrInfo()), IPA(lis, MF.getNumBlockIDs()) {} 379 TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()), 523 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); 549 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
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H A D | MachineFunction.cpp | 348 const TargetInstrInfo *TII = getSubtarget().getInstrInfo(); local 359 bool isRetBlock = MBBI->isReturnBlock() && !TII->isTailCall(MBBI->back());
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H A D | RDFGraph.cpp | 600 return TII.isPredicated(In); 654 : MF(mf), TII(tii), TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(toi),
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H A D | LiveIntervals.cpp | 127 TII = MF->getSubtarget().getInstrInfo();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRExpandPseudoInsts.cpp | 51 const TargetInstrInfo *TII; member in class:__anon4064::AVRExpandPseudo 65 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode)); 70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); 117 TII = STI.getInstrInfo();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBlockRanges.cpp | 221 TII(*HST.getInstrInfo()), TRI(*HST.getRegisterInfo()),
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H A D | HexagonInstrInfo.cpp | 687 const HexagonInstrInfo *TII; member in class:__anon4137::HexagonPipelinerLoopInfo 695 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()), 716 unsigned Done = TII->createVR(MF, MVT::i1); 718 TII->get(Hexagon::C2_cmpgtui), Done) 748 Register NewLoopCount = TII->createVR(MF, MVT::i32); 750 TII->get(Hexagon::A2_addi), NewLoopCount) 1354 CrashPseudoSourceValue(const TargetInstrInfo &TII) argument 1355 : PseudoSourceValue(TargetCustom, TII) {}
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H A D | HexagonBitTracker.cpp | 44 : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) { 986 // We need to evaluate one branch at a time. TII::analyzeBranch checks 1060 if (TII.isPredicated(MI))
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H A D | HexagonISelDAGToDAGHVX.cpp | 734 const TargetInstrInfo &TII = *G.getSubtarget().getInstrInfo(); 736 << TII.getName(Opc);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 198 TII(Subtarget.getInstrInfo()) { 862 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), 924 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), 929 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), 955 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), 1024 BuildMI(MBB, MBB.end(), DL, TII->get(MovTermOpc), SaveExecReg) 1560 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this)) 1829 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
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H A D | SIMachineScheduler.cpp | 1799 SITII = static_cast<const SIInstrInfo*>(TII);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 482 auto &TII = *MI.getMF()->getSubtarget().getInstrInfo(); 484 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 2172 auto &TII = *MI.getMF()->getSubtarget().getInstrInfo(); local 2173 MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2366 const auto &TII = MIRBuilder.getTII(); local 2367 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 4273 auto &TII = *MI.getMF()->getSubtarget().getInstrInfo(); local 4284 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 4334 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 4373 MI.setDesc(TII [all...] |
H A D | IRTranslator.cpp | 1673 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 1674 HasTailCall = TII->isTailCall(*std::prev(MIRBuilder.getInsertPt())); 1682 auto TII = MF->getTarget().getIntrinsicInfo(); 1701 if (TII && ID == Intrinsic::not_intrinsic) 1702 ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
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H A D | MachineIRBuilder.cpp | 30 State.TII = MF.getSubtarget().getInstrInfo();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1527 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local 1561 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1577 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 753 const SystemZInstrInfo *TII = getInstrInfo(); local 757 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 117 assert(DAG->TII && "No InstrInfo?"); 4539 const TargetInstrInfo *TII; 4547 TII(MF->getSubtarget().getInstrInfo()) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 3125 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); local 3159 BuildMI(ThisMBB, dl, TII.get(BROpcode)) 3167 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
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