Searched refs:TII (Results 226 - 250 of 403) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp57 const ARMBaseInstrInfo *TII; member in struct:__anon4007::A15SDOptimizer
423 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
440 TII->get(TargetOpcode::COPY), Out)
454 TII->get(TargetOpcode::REG_SEQUENCE), Out)
469 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
484 TII->get(TargetOpcode::INSERT_SUBREG), Out)
500 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
664 TII = STI.getInstrInfo();
H A DMVEVPTOptimisationsPass.cpp42 const Thumb2InstrInfo *TII; member in class:__anon4061::MVEVPTOptimisations
158 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT))
412 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT))
445 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
H A DThumb2ITBlockPass.cpp48 const Thumb2InstrInfo *TII; member in class:__anon4062::Thumb2ITBlock
214 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
291 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
H A DARMLoadStoreOptimizer.cpp105 const TargetInstrInfo *TII; member in struct:__anon4029::ARMLoadStoreOpt
552 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
573 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
743 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase)
746 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
756 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
761 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
767 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
806 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
818 MIB = BuildMI(MBB, InsertBefore, DL, TII
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h172 const TargetInstrInfo *TII; member in class:llvm::ModuloScheduleExpander
264 TII(ST.getInstrInfo()), LIS(LIS),
284 TII(ST.getInstrInfo()), LIS(LIS) {}
297 const TargetInstrInfo *TII; member in class:llvm::PeelingModuloScheduleExpander
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPrologEpilogInserter.cpp303 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
311 unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
312 unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
322 if (TII.isFrameInstr(*I)) {
323 unsigned Size = TII.getFrameSize(*I);
539 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
551 TII.get(TargetOpcode::COPY), CS.getDstReg())
555 TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC,
566 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
578 BuildMI(RestoreBlock, I, DebugLoc(), TII
1178 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
[all...]
H A DBBSectionsPrepare.cpp158 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local
170 TII->insertUnconditionalBranch(MBB, FTMBB, MBB.findBranchDebugLoc());
181 if (TII->analyzeBranch(MBB, TBB, FBB, Cond))
H A DGCRootLowering.cpp60 const TargetInstrInfo *TII; member in class:__anon3468::GCMachineCodeAnalysis
258 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
311 TII = MF.getSubtarget().getInstrInfo();
H A DMachineInstr.cpp93 const TargetInstrInfo *&TII) {
99 TII = MF->getSubtarget().getInstrInfo();
868 const TargetInstrInfo *TII,
876 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
907 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
915 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
919 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
925 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
932 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
937 const TargetInstrInfo *TII, cons
89 tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII) argument
906 getRegClassConstraintEffectForVReg( Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle) const argument
923 getRegClassConstraintEffectForVRegImpl( unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument
935 getRegClassConstraintEffect( unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument
1230 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local
[all...]
H A DStackSlotColoring.cpp64 const TargetInstrInfo *TII; member in class:__anon3592::StackSlotColoring
435 if (TII->isStackSlotCopy(*I, FirstSS, SecondSS) && FirstSS == SecondSS &&
450 if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize)))
458 if (!(StoreReg = TII->isStoreToStackSlot(*NextMI, SecondSS, StoreSize)))
493 TII = MF.getSubtarget().getInstrInfo();
H A DInlineSpiller.cpp95 const TargetInstrInfo &TII; member in class:__anon3482::HoistSpillHelper
147 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
168 const TargetInstrInfo &TII; member in class:__anon3482::InlineSpiller
203 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
302 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
306 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
413 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
472 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
475 MI.setDesc(TII.get(TargetOpcode::KILL));
732 Register InstrReg = TII
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H A DMIRPrinter.cpp168 const TargetRegisterInfo *TRI, const TargetInstrInfo *TII,
735 const auto *TII = SubTarget.getInstrInfo(); local
736 assert(TII && "Expected target instruction info");
748 print(MI, I, TRI, TII, ShouldPrintRegisterTies,
784 OS << TII->getName(MI.getOpcode());
792 print(MI, I, TRI, TII, ShouldPrintRegisterTies,
838 Op->print(OS, MST, SSNs, Context, &MFI, TII);
861 const TargetInstrInfo *TII,
865 std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
895 const TargetIntrinsicInfo *TII local
859 print(const MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, bool ShouldPrintRegisterTies, LLT TypeToPrint, bool PrintDef) argument
[all...]
H A DImplicitNullChecks.cpp164 const TargetInstrInfo *TII = nullptr; member in class:__anon3480::ImplicitNullChecks
298 TII = MF.getSubtarget().getInstrInfo();
371 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI) ||
480 if (TII->analyzeBranchPredicate(MBB, MBP, true))
644 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)
676 unsigned BranchesRemoved = TII->removeBranch(*NC.getCheckBlock());
718 TII->insertBranch(*NC.getCheckBlock(), NC.getNotNullSucc(), nullptr,
H A DMachineLICM.cpp119 const TargetInstrInfo *TII; member in class:__anon3512::MachineLICMBase
343 TII = ST.getInstrInfo();
517 (TII->isLoadFromStackSlot(*MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
867 if (!TII->analyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
1160 if (TII->hasHighOperandLatency(SchedModel, MRI, MI, DefIdx, UseMI, i))
1174 if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
1188 if (!TII->hasLowDefLatency(SchedModel, MI, i))
1268 if (TII->isTriviallyReMaterializable(MI, AA))
1321 if (!TII->isTriviallyReMaterializable(MI, AA) &&
1347 TII
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.h48 const HexagonInstrInfo &TII; member in struct:llvm::HexagonEvaluator
H A DHexagonSubtarget.cpp146 auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
265 const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
496 const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
508 if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
509 !TII->canExecuteInBundle(SrcInst, DstInst))
565 isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
573 isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
495 isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.h29 const R600InstrInfo *TII = nullptr; member in class:llvm::final
H A DAMDGPUMachineCFGStructurizer.cpp475 const SIInstrInfo *TII,
618 static unsigned createBBSelectReg(const SIInstrInfo *TII,
620 return MRI->createVirtualRegister(TII->getPreferredSelectRegClass(32));
638 const SIInstrInfo *TII, MachineRegisterInfo *MRI) {
649 unsigned BBSelectRegIn = createBBSelectReg(TII, MRI);
1091 const SIInstrInfo *TII;
1236 const SIInstrInfo *TII);
1278 TII->convertNonUniformIfRegion(Entry, Exit);
1486 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1531 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp68 const PPCInstrInfo *TII; member in struct:__anon4285::PPCVSXFMAMutate
75 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
260 MI.setDesc(TII->get(AltOpc));
357 TII = STI.getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMachineScheduler.h33 const SystemZInstrInfo *TII; member in class:llvm::SystemZPostRASchedStrategy
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp37 const TargetInstrInfo *TII; member in struct:__anon4173::Filler
50 TII = Subtarget.getInstrInfo();
126 BuildMI(MBB, std::next(I), DebugLoc(), TII->get(Lanai::NOP));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp39 const TargetInstrInfo *TII; member in class:__anon3845::AArch64DeadRegisterDefinitions
160 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
192 TII = MF.getSubtarget().getInstrInfo();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp150 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); local
172 TII->movImm(MBB, II, DL, ScratchReg, Offset);
173 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86EvexToVex.cpp87 const X86InstrInfo *TII = nullptr; member in class:__anon4425::EvexToVexInstPass
95 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
265 MI.setDesc(TII->get(NewOpc));
H A DX86VZeroUpper.cpp107 const TargetInstrInfo *TII; member in class:__anon4465::VZeroUpperInserter
186 BuildMI(MBB, I, dl, TII->get(X86::VZEROUPPER));
292 TII = ST.getInstrInfo();

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