Lines Matching refs:TII
93 const TargetInstrInfo *&TII) {
99 TII = MF->getSubtarget().getInstrInfo();
868 const TargetInstrInfo *TII,
876 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
907 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
915 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
919 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
925 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
932 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
937 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
938 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1230 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1243 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1527 const TargetInstrInfo *TII) const {
1533 if (!TII)
1534 TII = MF->getSubtarget().getInstrInfo();
1540 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1545 bool AddNewLine, const TargetInstrInfo *TII) const {
1550 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1617 if (TII)
1618 OS << TII->getName(getOpcode());
1783 Op->print(OS, MST, SSNs, *Context, MFI, TII);
2194 MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2196 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2205 MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2207 if (TII->hasStoreToStackSlot(*this, Accesses))
2213 MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2215 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2224 MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2226 if (TII->hasLoadFromStackSlot(*this, Accesses))