Searched refs:SUB (Results 51 - 75 of 89) sorted by relevance

1234

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp96 setOperationAction(ISD::SUB, VecTys[i], Legal);
344 setOperationAction(ISD::SUB, Ty, Legal);
826 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
2076 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2266 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2272 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
3419 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1500 setTargetDAGCombine(ISD::SUB);
4676 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4681 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4787 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
6049 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
6052 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
6091 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
6097 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
6146 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
6155 SDValue Bits = DAG.getNode(ISD::SUB, d
[all...]
H A DARMTargetTransformInfo.cpp149 // Conversion to SUB is free, and means we can use -Imm instead.
284 { ISD::SUB, MVT::v4i32, MVT::v4i16, 0 },
285 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 },
920 // Folded into a ADC/ADD/AND/BIC/CMP/EOR/MVN/ORR/ORN/RSB/SBC/SUB
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp176 // ADD, SUB overflow.
486 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
808 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
809 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
846 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
847 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
H A DAMDGPUISelDAGToDAG.cpp1174 } else if (Addr.getOpcode() == ISD::SUB) {
1184 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
1252 } else if (Addr.getOpcode() == ISD::SUB) {
1265 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
H A DAMDGPUTargetTransformInfo.cpp483 case ISD::SUB:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1298 case ISD::SUB:
1366 if (ISDOpcode == ISD::SUB)
1965 return SelectBinaryIntOp(I, ISD::SUB);
H A DPPCISelLowering.cpp635 setOperationAction(ISD::SUB, VT, Legal);
920 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
7936 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
8902 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
8931 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
8959 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
11045 SDValue Y = DAG.getNode(ISD::SUB, dl, VT, Zero, X);
13182 auto SubNode = DAG.getNode(ISD::SUB, DL, MVT::i64, Op0, Op1);
13815 if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
13821 if (RHS.getOpcode() == ISD::SUB
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp691 setTargetDAGCombine(ISD::SUB);
1883 return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0)) &&
2020 } else if (RHS.getOpcode() == ISD::SUB) {
3031 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
3042 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5776 } else if (TVal.getOpcode() == ISD::SUB) {
5777 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
6328 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
6341 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
6383 SDValue RevShAmt = DAG.getNode(ISD::SUB, d
[all...]
/freebsd-13-stable/contrib/byacc/test/btyacc/
H A Dbtyacc_demo.tab.c136 enum Operator { ADD, SUB, MUL, MOD, DIV, DEREF }; enumerator in enum:Operator
2024 { yyval.expr = build_expr(yystack.l_mark[-3].expr, SUB, yystack.l_mark[0].expr); }
H A Dquote_calc.tab.c172 #define SUB 260 macro
338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
H A Dquote_calc2.tab.c172 #define SUB 260 macro
338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
351 "expr : expr \"SUB\" expr",
357 "expr : \"SUB\" expr",
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp230 case ISD::SUB: return "sub";
H A DLegalizeDAG.cpp1611 ISD::ADD : ISD::SUB;
3004 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
3217 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3338 case ISD::SUB: {
3510 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
4359 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
H A DLegalizeVectorOps.cpp364 case ISD::SUB:
H A DSelectionDAGBuilder.cpp2403 SDValue SUB = DAG.getNode(ISD::SUB, dl, local
2405 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
2463 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2664 DAG.getNode(ISD::SUB, dl, VT, SwitchOp, DAG.getConstant(B.First, dl, VT));
4773 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
6280 SDValue NegShAmt = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
6287 SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
6297 SDValue InvShAmt = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, ShAmt);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp95 setOperationAction(ISD::SUB, MVT::i32, Legal);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp315 BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg)
H A DRISCVFrameLowering.cpp184 Opc = RISCV::SUB;
H A DRISCVISelLowering.cpp120 setOperationAction(ISD::SUB, MVT::i32, Custom);
797 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
847 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
977 case ISD::SUB:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1979 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1983 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2039 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2043 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4541 return DAG.getNode(ISD::SUB, DL, VT, Num,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1109 X86_INTRINSIC_DATA(subborrow_32, ADX, X86ISD::SBB, X86ISD::SUB),
1110 X86_INTRINSIC_DATA(subborrow_64, ADX, X86ISD::SBB, X86ISD::SUB),
H A DX86FastISel.cpp2894 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break;
2896 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break;
2916 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) &&
2920 bool IsDec = BaseOpc == ISD::SUB;
H A DX86ISelLowering.h392 SUB,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1604 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1675 setOperationAction(ISD::SUB, NativeVT, Legal);
2963 SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});

Completed in 718 milliseconds

1234