Lines Matching refs:SUB
1500 setTargetDAGCombine(ISD::SUB);
4676 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4681 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4787 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
6049 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
6052 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
6091 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
6097 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
6146 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
6155 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
6167 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
6182 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
6317 ISD::SUB, dl, ShiftVT, getZeroVector(ShiftVT, DAG, dl), N->getOperand(1));
6356 ShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
6596 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
8853 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
8864 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
9154 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
9167 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
12352 case ISD::SUB:
12447 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
12478 SDValue Negate = DCI.DAG.getNode(ISD::SUB, dl, MVT::i32,
12509 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
12512 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
12640 Res = DAG.getNode(ISD::SUB, DL, VT,
12652 Res = DAG.getNode(ISD::SUB, DL, VT,
12666 Res = DAG.getNode(ISD::SUB, DL, VT,
15787 // CMOV 0, 1, ==, (CMPZ x, y) -> SRL (CTLZ (SUB x, y)), 5
15788 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
15793 // (ADDCARRY (SUB x, y), t:0, t:1)
15794 // where t = (SUBCARRY 0, (SUB x, y), 0)
15801 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
15807 DAG.getNode(ISD::SUB, dl, MVT::i32,
15843 // t1 = (USUBO (SUB x, y), 1)
15844 // t2 = (SUBCARRY (SUB x, y), t1:0, t1:1)
15927 case ISD::SUB: return PerformSUBCombine(N, DCI, Subtarget);
16418 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
16750 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
16809 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
16834 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
17498 // prints the negated value, for use with SUB instructions. It is
17541 // for 3-operand ADD/SUB immediate instructions.
17547 // modifier that prints the negated value, for use with SUB
17555 // modifier that prints the negated value, for use with SUB
17589 // ADD/SUB sp = sp + immediate.
17674 SDValue Rem = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul);
17765 SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);