/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiRegisterInfo.cpp | 209 // LPAC::SUB with the already negated offset. 212 MI.getOperand(3).setImm(LPAC::SUB);
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H A D | LanaiISelLowering.cpp | 142 setTargetDAGCombine(ISD::SUB); 964 Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op); 1030 SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size); 1252 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 1262 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 1306 ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); 1456 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 1481 case ISD::SUB:
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H A D | LanaiMemAluCombiner.cpp | 209 return LPAC::SUB;
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/freebsd-13-stable/sys/contrib/libsodium/src/libsodium/crypto_generichash/blake2b/ref/ |
H A D | blake2b-compress-avx2.h | 31 #define SUB(a, b) _mm256_sub_epi64(a, b) macro
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1579 case ISD::SUB: return visitSUB(N); 1735 case ISD::SUB: 2084 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 2119 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit); 2125 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 2156 DAG.FoldConstantArithmetic(IsAdd ? ISD::ADD : ISD::SUB, DL, VT, 2204 if (N0.getOpcode() == ISD::SUB && 2207 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N0.getOperand(1)}); 2213 if (N0.getOpcode() == ISD::SUB && 2218 return DAG.getNode(ISD::SUB, D [all...] |
H A D | TargetLowering.cpp | 2144 case ISD::SUB: { 2748 case ISD::SUB: 3314 assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && 3379 DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) && 3380 !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } )) 4064 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 4112 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 4136 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 4381 if (OpCode == ISD::ADD || OpCode == ISD::SUB) { 5140 SDValue NPQ = DAG.getNode(ISD::SUB, d [all...] |
H A D | LegalizeIntegerTypes.cpp | 133 case ISD::SUB: 489 ISD::SUB, dl, NVT, Op, 707 // 3. [US][ADD|SUB]SAT 760 return DAG.getNode(ISD::SUB, dl, PromotedType, Max, Op2Promoted); 771 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; 957 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 1168 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 2001 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 2261 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 2262 SDValue AmtLack = DAG.getNode(ISD::SUB, d [all...] |
H A D | SelectionDAGBuilder.h | 694 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 374 User->getOpcode() == X86ISD::SUB || 375 User->getOpcode() == ISD::SUB) { 581 case X86ISD::SUB: 626 // ADD/SUB with can negate the immediate and use the opposite operation 628 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB) && 632 if ((U->getOpcode() == X86ISD::ADD || U->getOpcode() == X86ISD::SUB) && 823 if ((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 837 unsigned NewOpcode = N->getOpcode() == ISD::ADD ? ISD::SUB : ISD::ADD; 2189 case ISD::SUB: { 2584 case X86ISD::SUB [all...] |
H A D | X86TargetTransformInfo.cpp | 224 { ISD::SUB, MVT::v2i64, 4 }, 734 { ISD::SUB, MVT::v32i8, 1 }, // psubb 736 { ISD::SUB, MVT::v16i16, 1 }, // psubw 738 { ISD::SUB, MVT::v8i32, 1 }, // psubd 740 { ISD::SUB, MVT::v4i64, 1 }, // psubq 775 { ISD::SUB, MVT::v32i8, 4 }, 777 { ISD::SUB, MVT::v16i16, 4 }, 779 { ISD::SUB, MVT::v8i32, 4 }, 781 { ISD::SUB, MVT::v4i64, 4 }, 916 { ISD::SUB, MV [all...] |
H A D | X86ISelLowering.cpp | 1068 setOperationAction(ISD::SUB, MVT::i16, Custom); 1069 setOperationAction(ISD::SUB, MVT::i32, Custom); 1276 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom); 1425 setOperationAction(ISD::SUB, VT, Custom); 1573 setOperationAction(ISD::SUB, MVT::v32i16, HasBWI ? Legal : Custom); 1575 setOperationAction(ISD::SUB, MVT::v64i8, HasBWI ? Legal : Custom); 1801 setOperationAction(ISD::SUB, VT, Custom); 1973 setTargetDAGCombine(ISD::SUB); 9098 /// is equal to ISD::SUB, then this function checks if this is a horizontal 9485 case ISD::SUB [all...] |
/freebsd-13-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-c64xplus.pl | 134 || SUB A0,1,A0 261 || [B0] SUB B0,1,B0 320 || [B1] SUB B1,1,B1
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H A D | sha1-c64xplus.pl | 89 || SUB A0,1,A0
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H A D | sha256-c64xplus.pl | 109 SUB A0,1,A0
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 97 setOperationAction(ISD::SUB, MVT::i64, Custom); 215 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 239 case ISD::SUB: 697 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 1686 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, 1701 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
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/freebsd-13-stable/contrib/byacc/test/yacc/ |
H A D | quote_calc.tab.c | 152 #define SUB 260 macro 272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
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H A D | quote_calc2.tab.c | 152 #define SUB 260 macro 272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV", 285 "expr : expr \"SUB\" expr", 291 "expr : \"SUB\" expr",
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 652 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 676 if (N.getOpcode() == ISD::SUB) 725 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 739 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add; 765 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && 891 if (N.getOpcode() == ISD::SUB) { 1236 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) { 1241 if (N.getOpcode() == ISD::SUB) 1266 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 1296 if (N.getOpcode() == ISD::SUB) [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 419 case ISD::SUB:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 259 SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src);
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/freebsd-13-stable/crypto/openssl/crypto/aes/asm/ |
H A D | aes-c64xplus.pl | 139 SUB B0,2,B0 351 SUB B0,2,B0 800 || [B0] SUB B0,1,B0 854 [B0] SUB B1,1,B1 873 || SUB $KPB,A0,$KPB 885 SUB B0,1,B0 ; skip last round 899 || SUB B0,1,B0 975 || [B0] SUB B0,1,B0 1031 || [A2] SUB A2,1,A2 ; $blocks--
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 89 setOperationAction(ISD::SUB, T, Legal); 158 setOperationAction(ISD::SUB, T, Legal); 765 SDValue SubV = DAG.getNode(ISD::SUB, dl, MVT::i32, 958 SDValue S = DAG.getNode(ISD::SUB, dl, MVT::i32, IdxV, HalfV); 992 SDValue RolV = DAG.getNode(ISD::SUB, dl, MVT::i32, 1044 SDValue ByteXdi = DAG.getNode(ISD::SUB, dl, MVT::i32, HwLenV, ByteIdx); 1367 DAG.getNode(ISD::SUB, dl, ResTy, {InpV, Vec1})}); 1368 return DAG.getNode(ISD::SUB, dl, ResTy,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 437 setOperationAction(ISD::SUB, VT, Expand); 1731 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem); 1819 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); 1860 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); 1953 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS); 1989 SDValue NegY = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Y); 1997 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y)); 2006 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); 2013 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); 2068 Div = DAG.getNode(ISD::SUB, D [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 724 ISD::SUB, DL, N->getValueType(0), N->getOperand(0), 801 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 807 if (Op->getOpcode() == ISD::SUB) 852 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 858 if (Op->getOpcode() == ISD::SUB)
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/freebsd-13-stable/crypto/openssl/crypto/poly1305/asm/ |
H A D | poly1305-c64xplus.pl | 158 || [A2] SUB A2,1,A2 ; decrement loop counter
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