Lines Matching refs:SUB
1068 setOperationAction(ISD::SUB, MVT::i16, Custom);
1069 setOperationAction(ISD::SUB, MVT::i32, Custom);
1276 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1425 setOperationAction(ISD::SUB, VT, Custom);
1573 setOperationAction(ISD::SUB, MVT::v32i16, HasBWI ? Legal : Custom);
1575 setOperationAction(ISD::SUB, MVT::v64i8, HasBWI ? Legal : Custom);
1801 setOperationAction(ISD::SUB, VT, Custom);
1973 setTargetDAGCombine(ISD::SUB);
9098 /// is equal to ISD::SUB, then this function checks if this is a horizontal
9485 case ISD::SUB: HOpcode = X86ISD::HSUB; break;
9631 else if (isHorizontalBinOpPart(BV, ISD::SUB, DAG, 0, Half, InVec0,
9633 isHorizontalBinOpPart(BV, ISD::SUB, DAG, Half, NumElts, InVec2,
9665 else if (isHorizontalBinOpPart(BV, ISD::SUB, DAG, 0, NumElts, InVec0,
9717 // TODO: We may be able to add support for other Ops (ADD/SUB + shifts).
21136 case ISD::SUB: HOpcode = X86ISD::HSUB; break;
21631 case ISD::SUB:
21669 case ISD::SUB:
21679 case ISD::SUB: Opcode = X86ISD::SUB; break;
21688 case X86ISD::SUB:
21695 // /USUBO/SSUBO will become a X86ISD::SUB and we can use its Z flag.
21697 return DAG.getNode(X86ISD::SUB, dl, VTs, Op->getOperand(0),
21778 if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op0.getOperand(0)) &&
21787 if (Op1.getOpcode() == ISD::SUB && isNullConstant(Op1.getOperand(0)) &&
21794 // Use SUB instead of CMP to enable CSE between SUB and CMP.
21796 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, Op0, Op1);
21944 return DAG.getNode(ISD::SUB, DL, VT, Zero, SRA);
22881 BaseOp = X86ISD::SUB;
22885 BaseOp = X86ISD::SUB;
22930 (Opc == X86ISD::ADD || Opc == X86ISD::SUB || Opc == X86ISD::ADC ||
23071 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, CmpVTs, Zero, CmpOp0);
23076 Cmp = DAG.getNode(X86ISD::SUB, DL, CmpVTs,
23118 SDValue Mask = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
23187 if (Cond.getOpcode() == X86ISD::SUB) {
23835 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
24342 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
24344 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset);
24901 // If the carry in is zero, then we should just use ADD/SUB instead of
26108 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
26236 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
26457 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y);
26482 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
26494 DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Src);
26776 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Fixup);
27113 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
27182 Res = DAG.getNode(ISD::SUB, dl, VT, Res, SignMask);
27304 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
27332 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
27400 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt);
27419 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt);
27522 Amt = DAG.getNode(ISD::SUB, dl, ExVT, DAG.getConstant(8, dl, ExVT), Amt);
27904 AmtR = DAG.getNode(ISD::SUB, DL, VT, AmtR, Amt);
28647 RHS = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), RHS);
29319 case ISD::SUB: return lowerAddSub(Op, DAG, Subtarget);
30435 NODE_NAME_CASE(SUB)
38637 // (ABS (SUB (ZERO_EXTEND a), (ZERO_EXTEND b))).
38641 if (AbsOp1.getOpcode() != ISD::SUB)
38906 return DAG.getNode(ISD::SUB, DL, ExtractVT, Zero, Zext);
39831 if (!DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT))
39835 return N->getOpcode() == ISD::SUB && N->getOperand(1) == V &&
39851 // the operands of the SUB need to be swapped. PR 27251.
39863 SDValue Res = DAG.getNode(ISD::SUB, DL, MaskVT, SubOp1, SubOp2);
40190 Other->getOpcode() == ISD::SUB && OpRHS == CondRHS)
40206 OpRHS = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
40412 (Cmp.getOpcode() == X86ISD::SUB && !Cmp->hasAnyUseOfValue(0))))
40517 (Cmp.getOpcode() == X86ISD::SUB && !Cmp->hasAnyUseOfValue(0))))
40698 if (CarryOp1.getOpcode() == X86ISD::SUB &&
40703 DAG.getNode(X86ISD::SUB, SDLoc(CarryOp1), CarryOp1->getVTList(),
40859 if (CmpOpcode != X86ISD::CMP && CmpOpcode != X86ISD::SUB)
40886 bool IsAllOf = CmpOpcode == X86ISD::SUB && NumElts <= CmpBits &&
41150 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
41232 SDValue Diff = DAG.getNode(ISD::SUB, DL, VT, Const, Add.getOperand(1));
41386 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result,
41396 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result,
41603 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
41653 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
41672 NewMul = DAG.getNode(ISD::SUB, DL, VT,
41681 NewMul = DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), NewMul);
41683 NewMul = DAG.getNode(ISD::SUB, DL, VT, NewMul, N->getOperand(0));
41696 NewMul = DAG.getNode(ISD::SUB, DL, VT, NewMul, N->getOperand(0));
41697 NewMul = DAG.getNode(ISD::SUB, DL, VT, NewMul, N->getOperand(0));
42724 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, SizeC, Index);
43716 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], VecOnes);
44657 case ISD::SUB: {
46166 return DAG.getNode(ISD::SUB, DL, VT, Zext, DAG.getConstant(1, DL, VT));
47136 case ISD::SUB:
47140 NewOpc = X86ISD::SUB;
47163 assert((X86ISD::ADD == N->getOpcode() || X86ISD::SUB == N->getOpcode()) &&
47164 "Expected X86ISD::ADD or X86ISD::SUB");
47170 unsigned GenericOpc = X86ISD::ADD == N->getOpcode() ? ISD::ADD : ISD::SUB;
47172 // If we don't use the flag result, simplify back to a generic ADD/SUB.
47178 // Fold any similar generic ADD/SUB opcodes to reuse this node.
47185 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
47190 MatchGeneric(RHS, LHS, X86ISD::SUB == N->getOpcode());
47204 // Fold SBB(SUB(X,Y),0,Carry) -> SBB(X,Y,Carry)
47208 if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op1) &&
47251 /// then try to convert it to an ADC or SBB. This replaces TEST+SET+{ADD/SUB}
47254 bool IsSub = N->getOpcode() == ISD::SUB;
47302 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
47305 // Swap the operands of a SUB, and we have the same pattern as above.
47306 // -1 + SETBE (SUB A, B) --> -1 + SETAE (SUB B, A) --> SUB + SBB
47307 // 0 - SETA (SUB A, B) --> 0 - SETB (SUB B, A) --> SUB + SBB
47309 X86ISD::SUB, SDLoc(EFLAGS), EFLAGS.getNode()->getVTList(),
47335 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.getNode()->hasOneUse() &&
47338 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
47366 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.getNode()->hasOneUse() &&
47370 X86ISD::SUB, SDLoc(EFLAGS), EFLAGS.getNode()->getVTList(),
47402 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, X86SubVTs, Zero, Z);
47416 SDValue Cmp1 = DAG.getNode(X86ISD::SUB, DL, X86SubVTs, Z, One);
47426 SDValue Cmp1 = DAG.getNode(X86ISD::SUB, DL, X86SubVTs, Z, One);
47675 assert((IsAdd || N->getOpcode() == ISD::SUB) && "Wrong opcode");
47726 return DAG.getNode(ISD::SUB, DL, VT, Op1, SExt);
47734 return DAG.getNode(ISD::SUB, DL, VT, Op0, SExt);
47888 // Try to create PSUBUS if SUB's argument is max/min
48878 case ISD::SUB: return combineSub(N, DAG, DCI, Subtarget);
48880 case X86ISD::SUB: return combineX86AddSub(N, DAG, DCI);
49057 case ISD::SUB:
49146 case ISD::SUB: {