/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVFrameLowering.cpp | 121 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local 125 RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || 566 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local 576 int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), 577 RegInfo->getSpillAlign(*RC), false);
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H A D | RISCVISelLowering.cpp | 1217 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 1218 Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); 1788 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 1808 Register VReg = RegInfo.createVirtualRegister(RC); 1809 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1874 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 1886 Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); 1887 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); 1898 Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); 1899 RegInfo 2046 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineOperand.cpp | 239 MachineRegisterInfo *RegInfo = nullptr; local 241 RegInfo = &MF->getRegInfo(); 245 if (RegInfo && WasReg) 246 RegInfo->removeRegOperandFromUseList(this); 270 if (RegInfo) 271 RegInfo->addRegOperandToUseList(this);
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H A D | RDFRegisters.cpp | 35 RegInfo &RI = RegInfos[R]; 231 const RegInfo &RI = RegInfos[R];
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H A D | StackMaps.cpp | 350 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo(); local 352 MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(*(AP.MF));
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H A D | MachineBasicBlock.cpp | 126 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 129 I->AddRegOperandsToUseLists(RegInfo);
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H A D | RegAllocGreedy.cpp | 237 // RegInfo - Keep additional information about each live range. 238 struct RegInfo { struct in class:__anon3553::RAGreedy 244 RegInfo() = default; 247 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGISel.h | 46 MachineRegisterInfo *RegInfo; member in class:llvm::SelectionDAGISel
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H A D | MachineFunction.h | 234 // RegInfo - Information about each register in use in the function. 235 MachineRegisterInfo *RegInfo; member in class:llvm::MachineFunction 529 MachineRegisterInfo &getRegInfo() { return *RegInfo; } 530 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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H A D | TargetRegisterInfo.h | 1185 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 861 const MCRegisterInfo *RegInfo; member in struct:__anon4201::MipsOperand::RegIdxOp 890 const MCRegisterInfo *RegInfo, 895 Op->RegIdx.RegInfo = RegInfo; 911 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 919 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 927 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 937 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) 945 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) 953 return RegIdx.RegInfo 888 CreateReg(unsigned Index, StringRef Str, RegKind RegKind, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1504 createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1513 createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1521 createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1529 createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1537 createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1545 createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1553 createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument 1561 createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 784 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local 786 RegInfo->getFrameRegister(MF), MVT::i32); 830 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local 832 RegInfo->getFrameRegister(MF), MVT::i32); 1267 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 1314 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1315 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1365 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1366 RegInfo.addLiveIn(ArgRegs[i], VReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 87 RegInfo = &MF->getRegInfo(); 369 return RegInfo->createVirtualRegister(
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H A D | SelectionDAGISel.cpp | 436 RegInfo = &MF->getRegInfo(); 547 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII); 568 for (std::pair<unsigned, unsigned> LI : RegInfo->liveins()) 581 MachineInstr *Def = RegInfo->getVRegDef(Reg); 596 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 616 UI = RegInfo->use_instr_begin(LDI->second), 617 E = RegInfo->use_instr_end(); UI != E; ) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InlineAsmLowering.cpp | 124 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 136 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 480 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 484 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 11384 MachineRegisterInfo &RegInfo = F->getRegInfo(); local 11386 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass 11419 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 11488 MachineRegisterInfo &RegInfo = F->getRegInfo(); local 11493 Register PtrReg = RegInfo.createVirtualRegister(RC); 11494 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC); 11496 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC); 11497 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC); 11498 Register MaskReg = RegInfo.createVirtualRegister(GPRC); 11499 Register Mask2Reg = RegInfo 12245 MachineRegisterInfo &RegInfo = F->getRegInfo(); local 12494 MachineRegisterInfo &RegInfo = F->getRegInfo(); local 12661 MachineRegisterInfo &RegInfo = F->getRegInfo(); local 12687 MachineRegisterInfo &RegInfo = F->getRegInfo(); local 12700 MachineRegisterInfo &RegInfo = F->getRegInfo(); local 12810 MachineRegisterInfo &RegInfo = F->getRegInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 1108 const MCRegisterInfo *RegInfo = Context.getRegisterInfo(); local 1111 FrameReg = RegInfo->getEncodingValue(StackReg); 1113 ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 71 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); local 72 return *(RegInfo->getRegClass(RC).begin() + RegNo);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 443 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 463 Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass); 464 RegInfo.addLiveIn(VA.getLocReg(), VReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1248 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); local 1249 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( 1250 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && 1256 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1258 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass) 1259 // : RegInfo.createVirtualRegister(&X86::GR32RegClass); 1264 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 1265 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1329 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 1331 InRegLEA2 = RegInfo 8538 MachineRegisterInfo &RegInfo = MF.getRegInfo(); variable 8700 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.cpp | 83 RegInfo(getHwMode()), TLInfo(TM, *this),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUPALMetadata.cpp | 265 static const struct RegInfo { struct
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/IPO/ |
H A D | PartialInlining.cpp | 537 FunctionOutliningMultiRegionInfo::OutlineRegionInfo RegInfo( 539 OutliningInfo->ORI.push_back(RegInfo);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 623 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); local 640 Register Reg = RegInfo.createVirtualRegister(RC);
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