Searched refs:RegInfo (Results 51 - 75 of 90) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp121 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
125 RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
566 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
576 int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
577 RegInfo->getSpillAlign(*RC), false);
H A DRISCVISelLowering.cpp1217 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
1218 Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1788 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
1808 Register VReg = RegInfo.createVirtualRegister(RC);
1809 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1874 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
1886 Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1887 RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
1898 Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1899 RegInfo
2046 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineOperand.cpp239 MachineRegisterInfo *RegInfo = nullptr; local
241 RegInfo = &MF->getRegInfo();
245 if (RegInfo && WasReg)
246 RegInfo->removeRegOperandFromUseList(this);
270 if (RegInfo)
271 RegInfo->addRegOperandToUseList(this);
H A DRDFRegisters.cpp35 RegInfo &RI = RegInfos[R];
231 const RegInfo &RI = RegInfos[R];
H A DStackMaps.cpp350 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo(); local
352 MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(*(AP.MF));
H A DMachineBasicBlock.cpp126 MachineRegisterInfo &RegInfo = MF.getRegInfo();
129 I->AddRegOperandsToUseLists(RegInfo);
H A DRegAllocGreedy.cpp237 // RegInfo - Keep additional information about each live range.
238 struct RegInfo { struct in class:__anon3553::RAGreedy
244 RegInfo() = default;
247 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGISel.h46 MachineRegisterInfo *RegInfo; member in class:llvm::SelectionDAGISel
H A DMachineFunction.h234 // RegInfo - Information about each register in use in the function.
235 MachineRegisterInfo *RegInfo; member in class:llvm::MachineFunction
529 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
530 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
H A DTargetRegisterInfo.h1185 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp861 const MCRegisterInfo *RegInfo; member in struct:__anon4201::MipsOperand::RegIdxOp
890 const MCRegisterInfo *RegInfo,
895 Op->RegIdx.RegInfo = RegInfo;
911 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
919 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
927 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
937 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
945 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
953 return RegIdx.RegInfo
888 CreateReg(unsigned Index, StringRef Str, RegKind RegKind, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1504 createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1513 createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1521 createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1529 createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1537 createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1545 createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1553 createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
1561 createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp784 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
786 RegInfo->getFrameRegister(MF), MVT::i32);
830 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
832 RegInfo->getFrameRegister(MF), MVT::i32);
1267 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
1314 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1315 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1365 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1366 RegInfo.addLiveIn(ArgRegs[i], VReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp87 RegInfo = &MF->getRegInfo();
369 return RegInfo->createVirtualRegister(
H A DSelectionDAGISel.cpp436 RegInfo = &MF->getRegInfo();
547 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
568 for (std::pair<unsigned, unsigned> LI : RegInfo->liveins())
581 MachineInstr *Def = RegInfo->getVRegDef(Reg);
596 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
616 UI = RegInfo->use_instr_begin(LDI->second),
617 E = RegInfo->use_instr_end(); UI != E; ) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp124 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
136 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp480 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
484 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11384 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
11386 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
11419 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
11488 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
11493 Register PtrReg = RegInfo.createVirtualRegister(RC);
11494 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC);
11496 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC);
11497 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC);
11498 Register MaskReg = RegInfo.createVirtualRegister(GPRC);
11499 Register Mask2Reg = RegInfo
12245 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
12494 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
12661 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
12687 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
12700 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
12810 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp1108 const MCRegisterInfo *RegInfo = Context.getRegisterInfo(); local
1111 FrameReg = RegInfo->getEncodingValue(StackReg);
1113 ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp71 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); local
72 return *(RegInfo->getRegClass(RC).begin() + RegNo);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp443 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
463 Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
464 RegInfo.addLiveIn(VA.getLocReg(), VReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1248 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); local
1249 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1250 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1256 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1258 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1259 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1264 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1265 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1329 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1331 InRegLEA2 = RegInfo
8538 MachineRegisterInfo &RegInfo = MF.getRegInfo(); variable
8700 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp83 RegInfo(getHwMode()), TLInfo(TM, *this),
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp265 static const struct RegInfo { struct
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DPartialInlining.cpp537 FunctionOutliningMultiRegionInfo::OutlineRegionInfo RegInfo(
539 OutliningInfo->ORI.push_back(RegInfo);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp623 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); local
640 Register Reg = RegInfo.createVirtualRegister(RC);

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