1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Methods common to all machine operands.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineOperand.h"
14#include "llvm/ADT/FoldingSet.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/Analysis/Loads.h"
17#include "llvm/Analysis/MemoryLocation.h"
18#include "llvm/CodeGen/MIRFormatter.h"
19#include "llvm/CodeGen/MIRPrinter.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineJumpTableInfo.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetRegisterInfo.h"
25#include "llvm/Config/llvm-config.h"
26#include "llvm/IR/Constants.h"
27#include "llvm/IR/IRPrintingPasses.h"
28#include "llvm/IR/Instructions.h"
29#include "llvm/IR/ModuleSlotTracker.h"
30#include "llvm/MC/MCDwarf.h"
31#include "llvm/Target/TargetIntrinsicInfo.h"
32#include "llvm/Target/TargetMachine.h"
33
34using namespace llvm;
35
36static cl::opt<int>
37    PrintRegMaskNumRegs("print-regmask-num-regs",
38                        cl::desc("Number of registers to limit to when "
39                                 "printing regmask operands in IR dumps. "
40                                 "unlimited = -1"),
41                        cl::init(32), cl::Hidden);
42
43static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
44  if (const MachineInstr *MI = MO.getParent())
45    if (const MachineBasicBlock *MBB = MI->getParent())
46      if (const MachineFunction *MF = MBB->getParent())
47        return MF;
48  return nullptr;
49}
50static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
51  return const_cast<MachineFunction *>(
52      getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
53}
54
55void MachineOperand::setReg(Register Reg) {
56  if (getReg() == Reg)
57    return; // No change.
58
59  // Clear the IsRenamable bit to keep it conservatively correct.
60  IsRenamable = false;
61
62  // Otherwise, we have to change the register.  If this operand is embedded
63  // into a machine function, we need to update the old and new register's
64  // use/def lists.
65  if (MachineFunction *MF = getMFIfAvailable(*this)) {
66    MachineRegisterInfo &MRI = MF->getRegInfo();
67    MRI.removeRegOperandFromUseList(this);
68    SmallContents.RegNo = Reg;
69    MRI.addRegOperandToUseList(this);
70    return;
71  }
72
73  // Otherwise, just change the register, no problem.  :)
74  SmallContents.RegNo = Reg;
75}
76
77void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
78                                  const TargetRegisterInfo &TRI) {
79  assert(Reg.isVirtual());
80  if (SubIdx && getSubReg())
81    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
82  setReg(Reg);
83  if (SubIdx)
84    setSubReg(SubIdx);
85}
86
87void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
88  assert(Reg.isPhysical());
89  if (getSubReg()) {
90    Reg = TRI.getSubReg(Reg, getSubReg());
91    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
92    // That won't happen in legal code.
93    setSubReg(0);
94    if (isDef())
95      setIsUndef(false);
96  }
97  setReg(Reg);
98}
99
100/// Change a def to a use, or a use to a def.
101void MachineOperand::setIsDef(bool Val) {
102  assert(isReg() && "Wrong MachineOperand accessor");
103  assert((!Val || !isDebug()) && "Marking a debug operation as def");
104  if (IsDef == Val)
105    return;
106  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
107  // MRI may keep uses and defs in different list positions.
108  if (MachineFunction *MF = getMFIfAvailable(*this)) {
109    MachineRegisterInfo &MRI = MF->getRegInfo();
110    MRI.removeRegOperandFromUseList(this);
111    IsDef = Val;
112    MRI.addRegOperandToUseList(this);
113    return;
114  }
115  IsDef = Val;
116}
117
118bool MachineOperand::isRenamable() const {
119  assert(isReg() && "Wrong MachineOperand accessor");
120  assert(Register::isPhysicalRegister(getReg()) &&
121         "isRenamable should only be checked on physical registers");
122  if (!IsRenamable)
123    return false;
124
125  const MachineInstr *MI = getParent();
126  if (!MI)
127    return true;
128
129  if (isDef())
130    return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
131
132  assert(isUse() && "Reg is not def or use");
133  return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
134}
135
136void MachineOperand::setIsRenamable(bool Val) {
137  assert(isReg() && "Wrong MachineOperand accessor");
138  assert(Register::isPhysicalRegister(getReg()) &&
139         "setIsRenamable should only be called on physical registers");
140  IsRenamable = Val;
141}
142
143// If this operand is currently a register operand, and if this is in a
144// function, deregister the operand from the register's use/def list.
145void MachineOperand::removeRegFromUses() {
146  if (!isReg() || !isOnRegUseList())
147    return;
148
149  if (MachineFunction *MF = getMFIfAvailable(*this))
150    MF->getRegInfo().removeRegOperandFromUseList(this);
151}
152
153/// ChangeToImmediate - Replace this operand with a new immediate operand of
154/// the specified value.  If an operand is known to be an immediate already,
155/// the setImm method should be used.
156void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
157  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
158
159  removeRegFromUses();
160
161  OpKind = MO_Immediate;
162  Contents.ImmVal = ImmVal;
163}
164
165void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
166  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
167
168  removeRegFromUses();
169
170  OpKind = MO_FPImmediate;
171  Contents.CFP = FPImm;
172}
173
174void MachineOperand::ChangeToES(const char *SymName,
175                                unsigned TargetFlags) {
176  assert((!isReg() || !isTied()) &&
177         "Cannot change a tied operand into an external symbol");
178
179  removeRegFromUses();
180
181  OpKind = MO_ExternalSymbol;
182  Contents.OffsetedInfo.Val.SymbolName = SymName;
183  setOffset(0); // Offset is always 0.
184  setTargetFlags(TargetFlags);
185}
186
187void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
188                                unsigned TargetFlags) {
189  assert((!isReg() || !isTied()) &&
190         "Cannot change a tied operand into a global address");
191
192  removeRegFromUses();
193
194  OpKind = MO_GlobalAddress;
195  Contents.OffsetedInfo.Val.GV = GV;
196  setOffset(Offset);
197  setTargetFlags(TargetFlags);
198}
199
200void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
201  assert((!isReg() || !isTied()) &&
202         "Cannot change a tied operand into an MCSymbol");
203
204  removeRegFromUses();
205
206  OpKind = MO_MCSymbol;
207  Contents.Sym = Sym;
208}
209
210void MachineOperand::ChangeToFrameIndex(int Idx) {
211  assert((!isReg() || !isTied()) &&
212         "Cannot change a tied operand into a FrameIndex");
213
214  removeRegFromUses();
215
216  OpKind = MO_FrameIndex;
217  setIndex(Idx);
218}
219
220void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
221                                         unsigned TargetFlags) {
222  assert((!isReg() || !isTied()) &&
223         "Cannot change a tied operand into a FrameIndex");
224
225  removeRegFromUses();
226
227  OpKind = MO_TargetIndex;
228  setIndex(Idx);
229  setOffset(Offset);
230  setTargetFlags(TargetFlags);
231}
232
233/// ChangeToRegister - Replace this operand with a new register operand of
234/// the specified value.  If an operand is known to be an register already,
235/// the setReg method should be used.
236void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
237                                      bool isKill, bool isDead, bool isUndef,
238                                      bool isDebug) {
239  MachineRegisterInfo *RegInfo = nullptr;
240  if (MachineFunction *MF = getMFIfAvailable(*this))
241    RegInfo = &MF->getRegInfo();
242  // If this operand is already a register operand, remove it from the
243  // register's use/def lists.
244  bool WasReg = isReg();
245  if (RegInfo && WasReg)
246    RegInfo->removeRegOperandFromUseList(this);
247
248  // Change this to a register and set the reg#.
249  assert(!(isDead && !isDef) && "Dead flag on non-def");
250  assert(!(isKill && isDef) && "Kill flag on def");
251  OpKind = MO_Register;
252  SmallContents.RegNo = Reg;
253  SubReg_TargetFlags = 0;
254  IsDef = isDef;
255  IsImp = isImp;
256  IsDeadOrKill = isKill | isDead;
257  IsRenamable = false;
258  IsUndef = isUndef;
259  IsInternalRead = false;
260  IsEarlyClobber = false;
261  IsDebug = isDebug;
262  // Ensure isOnRegUseList() returns false.
263  Contents.Reg.Prev = nullptr;
264  // Preserve the tie when the operand was already a register.
265  if (!WasReg)
266    TiedTo = 0;
267
268  // If this operand is embedded in a function, add the operand to the
269  // register's use/def list.
270  if (RegInfo)
271    RegInfo->addRegOperandToUseList(this);
272}
273
274/// isIdenticalTo - Return true if this operand is identical to the specified
275/// operand. Note that this should stay in sync with the hash_value overload
276/// below.
277bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
278  if (getType() != Other.getType() ||
279      getTargetFlags() != Other.getTargetFlags())
280    return false;
281
282  switch (getType()) {
283  case MachineOperand::MO_Register:
284    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
285           getSubReg() == Other.getSubReg();
286  case MachineOperand::MO_Immediate:
287    return getImm() == Other.getImm();
288  case MachineOperand::MO_CImmediate:
289    return getCImm() == Other.getCImm();
290  case MachineOperand::MO_FPImmediate:
291    return getFPImm() == Other.getFPImm();
292  case MachineOperand::MO_MachineBasicBlock:
293    return getMBB() == Other.getMBB();
294  case MachineOperand::MO_FrameIndex:
295    return getIndex() == Other.getIndex();
296  case MachineOperand::MO_ConstantPoolIndex:
297  case MachineOperand::MO_TargetIndex:
298    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
299  case MachineOperand::MO_JumpTableIndex:
300    return getIndex() == Other.getIndex();
301  case MachineOperand::MO_GlobalAddress:
302    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
303  case MachineOperand::MO_ExternalSymbol:
304    return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
305           getOffset() == Other.getOffset();
306  case MachineOperand::MO_BlockAddress:
307    return getBlockAddress() == Other.getBlockAddress() &&
308           getOffset() == Other.getOffset();
309  case MachineOperand::MO_RegisterMask:
310  case MachineOperand::MO_RegisterLiveOut: {
311    // Shallow compare of the two RegMasks
312    const uint32_t *RegMask = getRegMask();
313    const uint32_t *OtherRegMask = Other.getRegMask();
314    if (RegMask == OtherRegMask)
315      return true;
316
317    if (const MachineFunction *MF = getMFIfAvailable(*this)) {
318      // Calculate the size of the RegMask
319      const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
320      unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
321
322      // Deep compare of the two RegMasks
323      return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
324    }
325    // We don't know the size of the RegMask, so we can't deep compare the two
326    // reg masks.
327    return false;
328  }
329  case MachineOperand::MO_MCSymbol:
330    return getMCSymbol() == Other.getMCSymbol();
331  case MachineOperand::MO_CFIIndex:
332    return getCFIIndex() == Other.getCFIIndex();
333  case MachineOperand::MO_Metadata:
334    return getMetadata() == Other.getMetadata();
335  case MachineOperand::MO_IntrinsicID:
336    return getIntrinsicID() == Other.getIntrinsicID();
337  case MachineOperand::MO_Predicate:
338    return getPredicate() == Other.getPredicate();
339  case MachineOperand::MO_ShuffleMask:
340    return getShuffleMask() == Other.getShuffleMask();
341  }
342  llvm_unreachable("Invalid machine operand type");
343}
344
345// Note: this must stay exactly in sync with isIdenticalTo above.
346hash_code llvm::hash_value(const MachineOperand &MO) {
347  switch (MO.getType()) {
348  case MachineOperand::MO_Register:
349    // Register operands don't have target flags.
350    return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
351  case MachineOperand::MO_Immediate:
352    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
353  case MachineOperand::MO_CImmediate:
354    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
355  case MachineOperand::MO_FPImmediate:
356    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
357  case MachineOperand::MO_MachineBasicBlock:
358    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
359  case MachineOperand::MO_FrameIndex:
360    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
361  case MachineOperand::MO_ConstantPoolIndex:
362  case MachineOperand::MO_TargetIndex:
363    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
364                        MO.getOffset());
365  case MachineOperand::MO_JumpTableIndex:
366    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
367  case MachineOperand::MO_ExternalSymbol:
368    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
369                        StringRef(MO.getSymbolName()));
370  case MachineOperand::MO_GlobalAddress:
371    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
372                        MO.getOffset());
373  case MachineOperand::MO_BlockAddress:
374    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
375                        MO.getOffset());
376  case MachineOperand::MO_RegisterMask:
377  case MachineOperand::MO_RegisterLiveOut:
378    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
379  case MachineOperand::MO_Metadata:
380    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
381  case MachineOperand::MO_MCSymbol:
382    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
383  case MachineOperand::MO_CFIIndex:
384    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
385  case MachineOperand::MO_IntrinsicID:
386    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
387  case MachineOperand::MO_Predicate:
388    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
389  case MachineOperand::MO_ShuffleMask:
390    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
391  }
392  llvm_unreachable("Invalid machine operand type");
393}
394
395// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
396// it.
397static void tryToGetTargetInfo(const MachineOperand &MO,
398                               const TargetRegisterInfo *&TRI,
399                               const TargetIntrinsicInfo *&IntrinsicInfo) {
400  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
401    TRI = MF->getSubtarget().getRegisterInfo();
402    IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
403  }
404}
405
406static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
407  const auto *TII = MF.getSubtarget().getInstrInfo();
408  assert(TII && "expected instruction info");
409  auto Indices = TII->getSerializableTargetIndices();
410  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
411    return I.first == Index;
412  });
413  if (Found != Indices.end())
414    return Found->second;
415  return nullptr;
416}
417
418static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
419  auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
420  for (const auto &I : Flags) {
421    if (I.first == TF) {
422      return I.second;
423    }
424  }
425  return nullptr;
426}
427
428static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
429                             const TargetRegisterInfo *TRI) {
430  if (!TRI) {
431    OS << "%dwarfreg." << DwarfReg;
432    return;
433  }
434
435  if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
436    OS << printReg(*Reg, TRI);
437  else
438    OS << "<badreg>";
439}
440
441static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
442                                  ModuleSlotTracker &MST) {
443  OS << "%ir-block.";
444  if (BB.hasName()) {
445    printLLVMNameWithoutPrefix(OS, BB.getName());
446    return;
447  }
448  Optional<int> Slot;
449  if (const Function *F = BB.getParent()) {
450    if (F == MST.getCurrentFunction()) {
451      Slot = MST.getLocalSlot(&BB);
452    } else if (const Module *M = F->getParent()) {
453      ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
454      CustomMST.incorporateFunction(*F);
455      Slot = CustomMST.getLocalSlot(&BB);
456    }
457  }
458  if (Slot)
459    MachineOperand::printIRSlotNumber(OS, *Slot);
460  else
461    OS << "<unknown>";
462}
463
464static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
465                           SyncScope::ID SSID,
466                           SmallVectorImpl<StringRef> &SSNs) {
467  switch (SSID) {
468  case SyncScope::System:
469    break;
470  default:
471    if (SSNs.empty())
472      Context.getSyncScopeNames(SSNs);
473
474    OS << "syncscope(\"";
475    printEscapedString(SSNs[SSID], OS);
476    OS << "\") ";
477    break;
478  }
479}
480
481static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
482                                        unsigned TMMOFlag) {
483  auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
484  for (const auto &I : Flags) {
485    if (I.first == TMMOFlag) {
486      return I.second;
487    }
488  }
489  return nullptr;
490}
491
492static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
493                            const MachineFrameInfo *MFI) {
494  StringRef Name;
495  if (MFI) {
496    IsFixed = MFI->isFixedObjectIndex(FrameIndex);
497    if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
498      if (Alloca->hasName())
499        Name = Alloca->getName();
500    if (IsFixed)
501      FrameIndex -= MFI->getObjectIndexBegin();
502  }
503  MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
504}
505
506void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
507                                    const TargetRegisterInfo *TRI) {
508  OS << "%subreg.";
509  if (TRI)
510    OS << TRI->getSubRegIndexName(Index);
511  else
512    OS << Index;
513}
514
515void MachineOperand::printTargetFlags(raw_ostream &OS,
516                                      const MachineOperand &Op) {
517  if (!Op.getTargetFlags())
518    return;
519  const MachineFunction *MF = getMFIfAvailable(Op);
520  if (!MF)
521    return;
522
523  const auto *TII = MF->getSubtarget().getInstrInfo();
524  assert(TII && "expected instruction info");
525  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
526  OS << "target-flags(";
527  const bool HasDirectFlags = Flags.first;
528  const bool HasBitmaskFlags = Flags.second;
529  if (!HasDirectFlags && !HasBitmaskFlags) {
530    OS << "<unknown>) ";
531    return;
532  }
533  if (HasDirectFlags) {
534    if (const auto *Name = getTargetFlagName(TII, Flags.first))
535      OS << Name;
536    else
537      OS << "<unknown target flag>";
538  }
539  if (!HasBitmaskFlags) {
540    OS << ") ";
541    return;
542  }
543  bool IsCommaNeeded = HasDirectFlags;
544  unsigned BitMask = Flags.second;
545  auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
546  for (const auto &Mask : BitMasks) {
547    // Check if the flag's bitmask has the bits of the current mask set.
548    if ((BitMask & Mask.first) == Mask.first) {
549      if (IsCommaNeeded)
550        OS << ", ";
551      IsCommaNeeded = true;
552      OS << Mask.second;
553      // Clear the bits which were serialized from the flag's bitmask.
554      BitMask &= ~(Mask.first);
555    }
556  }
557  if (BitMask) {
558    // When the resulting flag's bitmask isn't zero, we know that we didn't
559    // serialize all of the bit flags.
560    if (IsCommaNeeded)
561      OS << ", ";
562    OS << "<unknown bitmask target flag>";
563  }
564  OS << ") ";
565}
566
567void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
568  OS << "<mcsymbol " << Sym << ">";
569}
570
571void MachineOperand::printStackObjectReference(raw_ostream &OS,
572                                               unsigned FrameIndex,
573                                               bool IsFixed, StringRef Name) {
574  if (IsFixed) {
575    OS << "%fixed-stack." << FrameIndex;
576    return;
577  }
578
579  OS << "%stack." << FrameIndex;
580  if (!Name.empty())
581    OS << '.' << Name;
582}
583
584void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
585  if (Offset == 0)
586    return;
587  if (Offset < 0) {
588    OS << " - " << -Offset;
589    return;
590  }
591  OS << " + " << Offset;
592}
593
594void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
595  if (Slot == -1)
596    OS << "<badref>";
597  else
598    OS << Slot;
599}
600
601static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
602                     const TargetRegisterInfo *TRI) {
603  switch (CFI.getOperation()) {
604  case MCCFIInstruction::OpSameValue:
605    OS << "same_value ";
606    if (MCSymbol *Label = CFI.getLabel())
607      MachineOperand::printSymbol(OS, *Label);
608    printCFIRegister(CFI.getRegister(), OS, TRI);
609    break;
610  case MCCFIInstruction::OpRememberState:
611    OS << "remember_state ";
612    if (MCSymbol *Label = CFI.getLabel())
613      MachineOperand::printSymbol(OS, *Label);
614    break;
615  case MCCFIInstruction::OpRestoreState:
616    OS << "restore_state ";
617    if (MCSymbol *Label = CFI.getLabel())
618      MachineOperand::printSymbol(OS, *Label);
619    break;
620  case MCCFIInstruction::OpOffset:
621    OS << "offset ";
622    if (MCSymbol *Label = CFI.getLabel())
623      MachineOperand::printSymbol(OS, *Label);
624    printCFIRegister(CFI.getRegister(), OS, TRI);
625    OS << ", " << CFI.getOffset();
626    break;
627  case MCCFIInstruction::OpDefCfaRegister:
628    OS << "def_cfa_register ";
629    if (MCSymbol *Label = CFI.getLabel())
630      MachineOperand::printSymbol(OS, *Label);
631    printCFIRegister(CFI.getRegister(), OS, TRI);
632    break;
633  case MCCFIInstruction::OpDefCfaOffset:
634    OS << "def_cfa_offset ";
635    if (MCSymbol *Label = CFI.getLabel())
636      MachineOperand::printSymbol(OS, *Label);
637    OS << CFI.getOffset();
638    break;
639  case MCCFIInstruction::OpDefCfa:
640    OS << "def_cfa ";
641    if (MCSymbol *Label = CFI.getLabel())
642      MachineOperand::printSymbol(OS, *Label);
643    printCFIRegister(CFI.getRegister(), OS, TRI);
644    OS << ", " << CFI.getOffset();
645    break;
646  case MCCFIInstruction::OpRelOffset:
647    OS << "rel_offset ";
648    if (MCSymbol *Label = CFI.getLabel())
649      MachineOperand::printSymbol(OS, *Label);
650    printCFIRegister(CFI.getRegister(), OS, TRI);
651    OS << ", " << CFI.getOffset();
652    break;
653  case MCCFIInstruction::OpAdjustCfaOffset:
654    OS << "adjust_cfa_offset ";
655    if (MCSymbol *Label = CFI.getLabel())
656      MachineOperand::printSymbol(OS, *Label);
657    OS << CFI.getOffset();
658    break;
659  case MCCFIInstruction::OpRestore:
660    OS << "restore ";
661    if (MCSymbol *Label = CFI.getLabel())
662      MachineOperand::printSymbol(OS, *Label);
663    printCFIRegister(CFI.getRegister(), OS, TRI);
664    break;
665  case MCCFIInstruction::OpEscape: {
666    OS << "escape ";
667    if (MCSymbol *Label = CFI.getLabel())
668      MachineOperand::printSymbol(OS, *Label);
669    if (!CFI.getValues().empty()) {
670      size_t e = CFI.getValues().size() - 1;
671      for (size_t i = 0; i < e; ++i)
672        OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
673      OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
674    }
675    break;
676  }
677  case MCCFIInstruction::OpUndefined:
678    OS << "undefined ";
679    if (MCSymbol *Label = CFI.getLabel())
680      MachineOperand::printSymbol(OS, *Label);
681    printCFIRegister(CFI.getRegister(), OS, TRI);
682    break;
683  case MCCFIInstruction::OpRegister:
684    OS << "register ";
685    if (MCSymbol *Label = CFI.getLabel())
686      MachineOperand::printSymbol(OS, *Label);
687    printCFIRegister(CFI.getRegister(), OS, TRI);
688    OS << ", ";
689    printCFIRegister(CFI.getRegister2(), OS, TRI);
690    break;
691  case MCCFIInstruction::OpWindowSave:
692    OS << "window_save ";
693    if (MCSymbol *Label = CFI.getLabel())
694      MachineOperand::printSymbol(OS, *Label);
695    break;
696  case MCCFIInstruction::OpNegateRAState:
697    OS << "negate_ra_sign_state ";
698    if (MCSymbol *Label = CFI.getLabel())
699      MachineOperand::printSymbol(OS, *Label);
700    break;
701  default:
702    // TODO: Print the other CFI Operations.
703    OS << "<unserializable cfi directive>";
704    break;
705  }
706}
707
708void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
709                           const TargetIntrinsicInfo *IntrinsicInfo) const {
710  print(OS, LLT{}, TRI, IntrinsicInfo);
711}
712
713void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
714                           const TargetRegisterInfo *TRI,
715                           const TargetIntrinsicInfo *IntrinsicInfo) const {
716  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
717  ModuleSlotTracker DummyMST(nullptr);
718  print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
719        /*IsStandalone=*/true,
720        /*ShouldPrintRegisterTies=*/true,
721        /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
722}
723
724void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
725                           LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
726                           bool IsStandalone, bool ShouldPrintRegisterTies,
727                           unsigned TiedOperandIdx,
728                           const TargetRegisterInfo *TRI,
729                           const TargetIntrinsicInfo *IntrinsicInfo) const {
730  printTargetFlags(OS, *this);
731  switch (getType()) {
732  case MachineOperand::MO_Register: {
733    Register Reg = getReg();
734    if (isImplicit())
735      OS << (isDef() ? "implicit-def " : "implicit ");
736    else if (PrintDef && isDef())
737      // Print the 'def' flag only when the operand is defined after '='.
738      OS << "def ";
739    if (isInternalRead())
740      OS << "internal ";
741    if (isDead())
742      OS << "dead ";
743    if (isKill())
744      OS << "killed ";
745    if (isUndef())
746      OS << "undef ";
747    if (isEarlyClobber())
748      OS << "early-clobber ";
749    if (Register::isPhysicalRegister(getReg()) && isRenamable())
750      OS << "renamable ";
751    // isDebug() is exactly true for register operands of a DBG_VALUE. So we
752    // simply infer it when parsing and do not need to print it.
753
754    const MachineRegisterInfo *MRI = nullptr;
755    if (Register::isVirtualRegister(Reg)) {
756      if (const MachineFunction *MF = getMFIfAvailable(*this)) {
757        MRI = &MF->getRegInfo();
758      }
759    }
760
761    OS << printReg(Reg, TRI, 0, MRI);
762    // Print the sub register.
763    if (unsigned SubReg = getSubReg()) {
764      if (TRI)
765        OS << '.' << TRI->getSubRegIndexName(SubReg);
766      else
767        OS << ".subreg" << SubReg;
768    }
769    // Print the register class / bank.
770    if (Register::isVirtualRegister(Reg)) {
771      if (const MachineFunction *MF = getMFIfAvailable(*this)) {
772        const MachineRegisterInfo &MRI = MF->getRegInfo();
773        if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
774          OS << ':';
775          OS << printRegClassOrBank(Reg, MRI, TRI);
776        }
777      }
778    }
779    // Print ties.
780    if (ShouldPrintRegisterTies && isTied() && !isDef())
781      OS << "(tied-def " << TiedOperandIdx << ")";
782    // Print types.
783    if (TypeToPrint.isValid())
784      OS << '(' << TypeToPrint << ')';
785    break;
786  }
787  case MachineOperand::MO_Immediate: {
788    const MIRFormatter *Formatter = nullptr;
789    if (const MachineFunction *MF = getMFIfAvailable(*this)) {
790      const auto *TII = MF->getSubtarget().getInstrInfo();
791      assert(TII && "expected instruction info");
792      Formatter = TII->getMIRFormatter();
793    }
794    if (Formatter)
795      Formatter->printImm(OS, *getParent(), OpIdx, getImm());
796    else
797      OS << getImm();
798    break;
799  }
800  case MachineOperand::MO_CImmediate:
801    getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
802    break;
803  case MachineOperand::MO_FPImmediate:
804    getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
805    break;
806  case MachineOperand::MO_MachineBasicBlock:
807    OS << printMBBReference(*getMBB());
808    break;
809  case MachineOperand::MO_FrameIndex: {
810    int FrameIndex = getIndex();
811    bool IsFixed = false;
812    const MachineFrameInfo *MFI = nullptr;
813    if (const MachineFunction *MF = getMFIfAvailable(*this))
814      MFI = &MF->getFrameInfo();
815    printFrameIndex(OS, FrameIndex, IsFixed, MFI);
816    break;
817  }
818  case MachineOperand::MO_ConstantPoolIndex:
819    OS << "%const." << getIndex();
820    printOperandOffset(OS, getOffset());
821    break;
822  case MachineOperand::MO_TargetIndex: {
823    OS << "target-index(";
824    const char *Name = "<unknown>";
825    if (const MachineFunction *MF = getMFIfAvailable(*this))
826      if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
827        Name = TargetIndexName;
828    OS << Name << ')';
829    printOperandOffset(OS, getOffset());
830    break;
831  }
832  case MachineOperand::MO_JumpTableIndex:
833    OS << printJumpTableEntryReference(getIndex());
834    break;
835  case MachineOperand::MO_GlobalAddress:
836    getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
837    printOperandOffset(OS, getOffset());
838    break;
839  case MachineOperand::MO_ExternalSymbol: {
840    StringRef Name = getSymbolName();
841    OS << '&';
842    if (Name.empty()) {
843      OS << "\"\"";
844    } else {
845      printLLVMNameWithoutPrefix(OS, Name);
846    }
847    printOperandOffset(OS, getOffset());
848    break;
849  }
850  case MachineOperand::MO_BlockAddress: {
851    OS << "blockaddress(";
852    getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
853                                                     MST);
854    OS << ", ";
855    printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
856    OS << ')';
857    MachineOperand::printOperandOffset(OS, getOffset());
858    break;
859  }
860  case MachineOperand::MO_RegisterMask: {
861    OS << "<regmask";
862    if (TRI) {
863      unsigned NumRegsInMask = 0;
864      unsigned NumRegsEmitted = 0;
865      for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
866        unsigned MaskWord = i / 32;
867        unsigned MaskBit = i % 32;
868        if (getRegMask()[MaskWord] & (1 << MaskBit)) {
869          if (PrintRegMaskNumRegs < 0 ||
870              NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
871            OS << " " << printReg(i, TRI);
872            NumRegsEmitted++;
873          }
874          NumRegsInMask++;
875        }
876      }
877      if (NumRegsEmitted != NumRegsInMask)
878        OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
879    } else {
880      OS << " ...";
881    }
882    OS << ">";
883    break;
884  }
885  case MachineOperand::MO_RegisterLiveOut: {
886    const uint32_t *RegMask = getRegLiveOut();
887    OS << "liveout(";
888    if (!TRI) {
889      OS << "<unknown>";
890    } else {
891      bool IsCommaNeeded = false;
892      for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
893        if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
894          if (IsCommaNeeded)
895            OS << ", ";
896          OS << printReg(Reg, TRI);
897          IsCommaNeeded = true;
898        }
899      }
900    }
901    OS << ")";
902    break;
903  }
904  case MachineOperand::MO_Metadata:
905    getMetadata()->printAsOperand(OS, MST);
906    break;
907  case MachineOperand::MO_MCSymbol:
908    printSymbol(OS, *getMCSymbol());
909    break;
910  case MachineOperand::MO_CFIIndex: {
911    if (const MachineFunction *MF = getMFIfAvailable(*this))
912      printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
913    else
914      OS << "<cfi directive>";
915    break;
916  }
917  case MachineOperand::MO_IntrinsicID: {
918    Intrinsic::ID ID = getIntrinsicID();
919    if (ID < Intrinsic::num_intrinsics)
920      OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
921    else if (IntrinsicInfo)
922      OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
923    else
924      OS << "intrinsic(" << ID << ')';
925    break;
926  }
927  case MachineOperand::MO_Predicate: {
928    auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
929    OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
930       << CmpInst::getPredicateName(Pred) << ')';
931    break;
932  }
933  case MachineOperand::MO_ShuffleMask:
934    OS << "shufflemask(";
935    ArrayRef<int> Mask = getShuffleMask();
936    StringRef Separator;
937    for (int Elt : Mask) {
938      if (Elt == -1)
939        OS << Separator << "undef";
940      else
941        OS << Separator << Elt;
942      Separator = ", ";
943    }
944
945    OS << ')';
946    break;
947  }
948}
949
950#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
951LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
952#endif
953
954//===----------------------------------------------------------------------===//
955// MachineMemOperand Implementation
956//===----------------------------------------------------------------------===//
957
958/// getAddrSpace - Return the LLVM IR address space number that this pointer
959/// points into.
960unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
961
962/// isDereferenceable - Return true if V is always dereferenceable for
963/// Offset + Size byte.
964bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
965                                           const DataLayout &DL) const {
966  if (!V.is<const Value *>())
967    return false;
968
969  const Value *BasePtr = V.get<const Value *>();
970  if (BasePtr == nullptr)
971    return false;
972
973  return isDereferenceableAndAlignedPointer(
974      BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
975}
976
977/// getConstantPool - Return a MachinePointerInfo record that refers to the
978/// constant pool.
979MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
980  return MachinePointerInfo(MF.getPSVManager().getConstantPool());
981}
982
983/// getFixedStack - Return a MachinePointerInfo record that refers to the
984/// the specified FrameIndex.
985MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
986                                                     int FI, int64_t Offset) {
987  return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
988}
989
990MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
991  return MachinePointerInfo(MF.getPSVManager().getJumpTable());
992}
993
994MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
995  return MachinePointerInfo(MF.getPSVManager().getGOT());
996}
997
998MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
999                                                int64_t Offset, uint8_t ID) {
1000  return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1001}
1002
1003MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1004  return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1005}
1006
1007MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1008                                     uint64_t s, Align a,
1009                                     const AAMDNodes &AAInfo,
1010                                     const MDNode *Ranges, SyncScope::ID SSID,
1011                                     AtomicOrdering Ordering,
1012                                     AtomicOrdering FailureOrdering)
1013    : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlign(a), AAInfo(AAInfo),
1014      Ranges(Ranges) {
1015  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1016          isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1017         "invalid pointer value");
1018  assert((isLoad() || isStore()) && "Not a load/store!");
1019
1020  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1021  assert(getSyncScopeID() == SSID && "Value truncated");
1022  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1023  assert(getOrdering() == Ordering && "Value truncated");
1024  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1025  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1026}
1027
1028/// Profile - Gather unique data for the object.
1029///
1030void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1031  ID.AddInteger(getOffset());
1032  ID.AddInteger(Size);
1033  ID.AddPointer(getOpaqueValue());
1034  ID.AddInteger(getFlags());
1035  ID.AddInteger(getBaseAlign().value());
1036}
1037
1038void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1039  // The Value and Offset may differ due to CSE. But the flags and size
1040  // should be the same.
1041  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1042  assert(MMO->getSize() == getSize() && "Size mismatch!");
1043
1044  if (MMO->getBaseAlign() >= getBaseAlign()) {
1045    // Update the alignment value.
1046    BaseAlign = MMO->getBaseAlign();
1047    // Also update the base and offset, because the new alignment may
1048    // not be applicable with the old ones.
1049    PtrInfo = MMO->PtrInfo;
1050  }
1051}
1052
1053/// getAlignment - Return the minimum known alignment in bytes of the
1054/// actual memory reference.
1055uint64_t MachineMemOperand::getAlignment() const { return getAlign().value(); }
1056
1057/// getAlign - Return the minimum known alignment in bytes of the
1058/// actual memory reference.
1059Align MachineMemOperand::getAlign() const {
1060  return commonAlignment(getBaseAlign(), getOffset());
1061}
1062
1063void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1064                              SmallVectorImpl<StringRef> &SSNs,
1065                              const LLVMContext &Context,
1066                              const MachineFrameInfo *MFI,
1067                              const TargetInstrInfo *TII) const {
1068  OS << '(';
1069  if (isVolatile())
1070    OS << "volatile ";
1071  if (isNonTemporal())
1072    OS << "non-temporal ";
1073  if (isDereferenceable())
1074    OS << "dereferenceable ";
1075  if (isInvariant())
1076    OS << "invariant ";
1077  if (getFlags() & MachineMemOperand::MOTargetFlag1)
1078    OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1079       << "\" ";
1080  if (getFlags() & MachineMemOperand::MOTargetFlag2)
1081    OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1082       << "\" ";
1083  if (getFlags() & MachineMemOperand::MOTargetFlag3)
1084    OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1085       << "\" ";
1086
1087  assert((isLoad() || isStore()) &&
1088         "machine memory operand must be a load or store (or both)");
1089  if (isLoad())
1090    OS << "load ";
1091  if (isStore())
1092    OS << "store ";
1093
1094  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1095
1096  if (getOrdering() != AtomicOrdering::NotAtomic)
1097    OS << toIRString(getOrdering()) << ' ';
1098  if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1099    OS << toIRString(getFailureOrdering()) << ' ';
1100
1101  if (getSize() == MemoryLocation::UnknownSize)
1102    OS << "unknown-size";
1103  else
1104    OS << getSize();
1105
1106  if (const Value *Val = getValue()) {
1107    OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1108    MIRFormatter::printIRValue(OS, *Val, MST);
1109  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1110    OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1111    assert(PVal && "Expected a pseudo source value");
1112    switch (PVal->kind()) {
1113    case PseudoSourceValue::Stack:
1114      OS << "stack";
1115      break;
1116    case PseudoSourceValue::GOT:
1117      OS << "got";
1118      break;
1119    case PseudoSourceValue::JumpTable:
1120      OS << "jump-table";
1121      break;
1122    case PseudoSourceValue::ConstantPool:
1123      OS << "constant-pool";
1124      break;
1125    case PseudoSourceValue::FixedStack: {
1126      int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1127      bool IsFixed = true;
1128      printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1129      break;
1130    }
1131    case PseudoSourceValue::GlobalValueCallEntry:
1132      OS << "call-entry ";
1133      cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1134          OS, /*PrintType=*/false, MST);
1135      break;
1136    case PseudoSourceValue::ExternalSymbolCallEntry:
1137      OS << "call-entry &";
1138      printLLVMNameWithoutPrefix(
1139          OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1140      break;
1141    default: {
1142      const MIRFormatter *Formatter = TII->getMIRFormatter();
1143      // FIXME: This is not necessarily the correct MIR serialization format for
1144      // a custom pseudo source value, but at least it allows
1145      // -print-machineinstrs to work on a target with custom pseudo source
1146      // values.
1147      OS << "custom \"";
1148      Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1149      OS << '\"';
1150      break;
1151    }
1152    }
1153  }
1154  MachineOperand::printOperandOffset(OS, getOffset());
1155  if (getBaseAlign() != getSize())
1156    OS << ", align " << getBaseAlign().value();
1157  auto AAInfo = getAAInfo();
1158  if (AAInfo.TBAA) {
1159    OS << ", !tbaa ";
1160    AAInfo.TBAA->printAsOperand(OS, MST);
1161  }
1162  if (AAInfo.Scope) {
1163    OS << ", !alias.scope ";
1164    AAInfo.Scope->printAsOperand(OS, MST);
1165  }
1166  if (AAInfo.NoAlias) {
1167    OS << ", !noalias ";
1168    AAInfo.NoAlias->printAsOperand(OS, MST);
1169  }
1170  if (getRanges()) {
1171    OS << ", !range ";
1172    getRanges()->printAsOperand(OS, MST);
1173  }
1174  // FIXME: Implement addrspace printing/parsing in MIR.
1175  // For now, print this even though parsing it is not available in MIR.
1176  if (unsigned AS = getAddrSpace())
1177    OS << ", addrspace " << AS;
1178
1179  OS << ')';
1180}
1181