Searched refs:ROTR (Results 26 - 49 of 49) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp404 // TODO: we may consider expanding ROTL/ROTR on older GPUs. Currently on GPUs
408 setOperationAction(ISD::ROTR, MVT::i64, Legal);
410 setOperationAction(ISD::ROTR, MVT::i32, Legal);
413 setOperationAction(ISD::ROTR, MVT::i16, Expand);
415 setOperationAction(ISD::ROTR, MVT::i8, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp625 setOperationAction(ISD::ROTR, IntVT, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1714 case ISD::ROTR: {
2780 case ISD::ROTR: {
5378 // We need ROTR to do this.
5379 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5384 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5630 // We need ROTR to do this.
5631 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5636 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
6229 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
H A DDAGCombiner.cpp1619 case ISD::ROTR:
5769 if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5799 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5863 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5864 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
6492 bool HasROTR = hasOperation(ISD::ROTR, VT);
6577 Res = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
6628 RExtOp0, ISD::ROTL, ISD::ROTR, DL);
6634 LExtOp0, ISD::ROTR, ISD::ROTL, DL);
7716 if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) {
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H A DSelectionDAG.cpp3813 case ISD::ROTR:
3825 if (Opcode == ISD::ROTR)
4856 case ISD::ROTR: return C1.rotr(C2);
5357 case ISD::ROTR:
9466 case ISD::ROTR:
H A DLegalizeDAG.cpp1179 case ISD::ROTR: {
3465 case ISD::ROTR:
H A DLegalizeIntegerTypes.cpp1395 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
3921 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
H A DSelectionDAGBuilder.cpp6270 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
6277 RotateOpcode = IsFSHL ? ISD::ROTR : ISD::ROTL;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp119 setOperationAction(ISD::ROTR, MVT::i32, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp459 case ISD::ROTR:
2737 case ISD::ROTR:
3359 case ISD::ROTR:
H A DAArch64ISelLowering.cpp389 setOperationAction(ISD::ROTR, VT, Expand);
11149 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
11152 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1627 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
H A DMipsISelLowering.cpp430 setOperationAction(ISD::ROTR, MVT::i32, Expand);
433 setOperationAction(ISD::ROTR, MVT::i64, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp167 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR})
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp109 setOperationAction(ISD::ROTR , MVT::i32, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1578 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1641 setOperationAction(ISD::ROTR , MVT::i32, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp394 // The hardware supports 32-bit ROTR, but not ROTL.
397 setOperationAction(ISD::ROTR, MVT::i64, Expand);
436 setOperationAction(ISD::ROTR, VT, Expand);
H A DSIISelLowering.cpp534 setOperationAction(ISD::ROTR, MVT::i16, Promote);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp154 setOperationAction(ISD::ROTR, XLenVT, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4941 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp398 // PowerPC does not have ROTR
399 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
400 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
731 setOperationAction(ISD::ROTR, VT, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp204 setOperationAction(ISD::ROTR, VT, Expand);
384 // At present ROTL isn't matched by DAGCombiner. ROTR should be
387 setOperationAction(ISD::ROTR, VT, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1143 setOperationAction(ISD::ROTR, VT, Expand);
15097 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp799 setOperationAction(ISD::ROTR, VT, Expand);
1610 setOperationAction(ISD::ROTR, VT, Custom);
1747 setOperationAction(ISD::ROTR, VT, Custom);
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