Searched refs:MUL (Results 26 - 50 of 79) sorted by relevance

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/freebsd-13-stable/contrib/byacc/test/yacc/
H A Dquote_calc.tab.c154 #define MUL 262 macro
272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
H A Dquote_calc2.tab.c154 #define MUL 262 macro
272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
286 "expr : expr \"MUL\" expr",
/freebsd-13-stable/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_scalar.c136 #define MUL(c, a) \ macro
H A Dvdev_raidz_math_avx512f.c368 #define MUL(c, r...) \ macro
H A Dvdev_raidz_math_aarch64_neon_common.h519 #define MUL(c, r...) \ macro
H A Dvdev_raidz_math_powerpc_altivec_common.h525 #define MUL(c, r...) \ macro
H A Dvdev_raidz_math_sse2.c505 #define MUL(c, r...) \ macro
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp100 setOperationAction(ISD::MUL, T, Custom);
159 setOperationAction(ISD::MUL, T, Custom);
741 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, ScV);
802 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, ScV);
969 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
1029 ByteIdx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
1404 // For i16 there is V6_vmpyih, which acts exactly like the MUL opcode.
1710 case ISD::MUL:
1745 case ISD::MUL: return LowerHvxMul(Op, DAG);
H A DHexagonISelLowering.cpp1604 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1676 setOperationAction(ISD::MUL, NativeVT, Legal);
2493 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2507 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2549 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2585 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2619 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h696 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
H A DLegalizeIntegerTypes.cpp134 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
1941 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
3090 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
3105 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
3110 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
3114 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
3121 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
3122 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3172 Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3703 SDValue Three = DAG.getNode(ISD::MUL, d
[all...]
H A DFastISel.cpp759 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
1862 return selectBinaryOp(I, ISD::MUL);
2035 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
H A DDAGCombiner.cpp1598 case ISD::MUL: return visitMUL(N);
1736 case ISD::MUL:
3218 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
3221 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3228 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3559 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT, {N0, N1}))
3565 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
3648 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
3668 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
3679 DAG.getNode(ISD::MUL, SDLo
[all...]
H A DLegalizeDAG.cpp3389 Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3413 case ISD::MUL: {
3616 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
4271 case ISD::MUL:
4421 case ISD::MUL:
4466 Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4692 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4740 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
H A DSelectionDAGDumper.cpp231 case ISD::MUL: return "mul";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp399 setOperationAction(ISD::MUL, MVT::i64, Expand);
428 setOperationAction(ISD::MUL, VT, Expand);
557 setTargetDAGCombine(ISD::MUL);
1730 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1820 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1835 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1852 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1990 SDValue NegYZ = DAG.getNode(ISD::MUL, DL, VT, NegY, Z);
1997 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y));
3988 case ISD::MUL
[all...]
H A DAMDGPUTargetTransformInfo.cpp496 case ISD::MUL: {
/freebsd-13-stable/contrib/byacc/test/btyacc/
H A Dbtyacc_demo.tab.c136 enum Operator { ADD, SUB, MUL, MOD, DIV, DEREF }; enumerator in enum:Operator
2029 { yyval.expr = build_expr(yystack.l_mark[-3].expr, MUL, yystack.l_mark[0].expr); }
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp287 { ISD::MUL, MVT::v4i32, MVT::v4i16, 0 },
288 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 },
H A DARMISelDAGToDAG.cpp536 assert(N.getOpcode() == ISD::MUL);
580 if (N.getOpcode() == ISD::MUL) {
701 if (N.getOpcode() == ISD::MUL &&
790 if (Offset.getOpcode() == ISD::MUL && N.hasOneUse()) {
1511 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) {
3455 case ISD::MUL:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp113 setOperationAction(ISD::MUL, MVT::i32, Custom);
178 case ISD::MUL:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp110 setOperationAction(ISD::MUL, MVT::i32, Legal);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp504 setTargetDAGCombine(ISD::MUL);
4334 if (N0.getOpcode() == ISD::MUL) {
4542 DAG.getNode(ISD::MUL, DL, VT,
4635 if (N->getOpcode() == ISD::MUL) {
4688 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4743 case ISD::MUL:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp885 setOperationAction(ISD::MUL, MVT::v2i8, Custom);
886 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
887 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
889 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
890 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
891 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
898 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
1098 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1279 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1280 setOperationAction(ISD::MUL, MV
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
163 setOperationAction(ISD::MUL, MVT::i8, Expand);
164 setOperationAction(ISD::MUL, MVT::i16, Expand);
171 // no hardware MUL.

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