Lines Matching refs:MUL
885 setOperationAction(ISD::MUL, MVT::v2i8, Custom);
886 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
887 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
889 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
890 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
891 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
898 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
1098 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1279 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1280 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1281 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1282 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1426 setOperationAction(ISD::MUL, VT, Custom);
1577 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1578 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1579 setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
1580 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1639 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1776 setOperationAction(ISD::MUL, VT, Legal);
1802 setOperationAction(ISD::MUL, VT, Custom);
1991 setTargetDAGCombine(ISD::MUL);
5182 if (isOperationLegal(ISD::MUL, VT))
9364 /// Returns true if is possible to fold MUL and an idiom that has already been
9400 // function that would answer if it is Ok to fuse MUL + ADD to FMADD
9401 // or MUL + ADDSUB to FMADDSUB.
9859 Idx = DAG.getNode(ISD::MUL, SDLoc(Idx), SrcVT, Idx,
21632 case ISD::MUL:
26581 DAG.getNode(ISD::MUL, dl, ExVT,
26617 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
26618 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
26799 SDValue Mul = DAG.getNode(ISD::MUL, dl, ExVT, ExA, ExB);
26883 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
26884 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
27393 return DAG.getNode(ISD::MUL, dl, VT, R, Scale);
27510 // extend to vXi16 to perform a MUL scale effectively as a MUL_LOHI.
27530 R = DAG.getNode(ISD::MUL, dl, ExVT, R, Amt);
27551 LoR = DAG.getNode(ISD::MUL, dl, VT16, LoR, LoA);
27552 HiR = DAG.getNode(ISD::MUL, dl, VT16, HiR, HiA);
27916 SDValue Lo = DAG.getNode(ISD::MUL, DL, VT, R, Scale);
29300 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
29432 case ISD::MUL: {
29441 SDValue Res = DAG.getNode(ISD::MUL, dl, MulVT, Op0, Op1);
39698 R = DAG.getNode(ISD::MUL, DL, VT, R, DAG.getConstant(AbsDiff, DL, VT));
41118 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
41343 SDValue MulLo = DAG.getNode(ISD::MUL, DL, ReducedVT, NewN0, NewN1);
41724 if (ShiftOperand.getOpcode() != ISD::MUL || !ShiftOperand.hasOneUse())
44645 case ISD::MUL:
44827 Src.getOperand(0).getOpcode() != ISD::MUL)
44897 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
47512 // First time an extract_elt's source vector is visited. Must be a MUL
47514 // Both extracts must be from same MUL.
47516 if (Mul->getOpcode() != ISD::MUL ||
47520 // Check that the extract is from the same MUL previously seen.
47557 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
48883 case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget);
49041 if ((Opc == ISD::MUL || Opc == ISD::SHL) && VT == MVT::i8)
49059 case ISD::MUL:
49089 bool Is8BitMulByConstant = VT == MVT::i8 && Op.getOpcode() == ISD::MUL &&
49140 case ISD::MUL:
49152 (Op.getOpcode() != ISD::MUL && IsFoldableRMW(N1, Op))))
49156 (Op.getOpcode() != ISD::MUL && IsFoldableRMW(N0, Op))))