Searched refs:AArch64 (Results 26 - 50 of 68) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
9 // This file contains the AArch64 implementation of the TargetRegisterInfo
39 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
92 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
94 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
106 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
107 return &AArch64::FPR32RegClass;
108 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64
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H A DAArch64AdvSIMDScalarPass.cpp35 #include "AArch64.h"
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
110 return AArch64::GPR64RegClass.contains(Reg);
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
119 SubReg == AArch64::dsub);
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
132 if (MI->getOpcode() == AArch64
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H A DAArch64A53Fix835769.cpp17 #include "AArch64.h"
42 case AArch64::PRFMl:
43 case AArch64::PRFMroW:
44 case AArch64::PRFMroX:
45 case AArch64::PRFMui:
46 case AArch64::PRFUMi:
61 case AArch64::MSUBXrrr:
62 case AArch64::MADDXrrr:
63 case AArch64::SMADDLrrr:
64 case AArch64
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H A DAArch64InstructionSelector.cpp10 /// AArch64.
335 if (RB.getID() == AArch64::GPRRegBankID) {
337 return GetAllRegSet ? &AArch64::GPR32allRegClass
338 : &AArch64::GPR32RegClass;
340 return GetAllRegSet ? &AArch64::GPR64allRegClass
341 : &AArch64::GPR64RegClass;
345 if (RB.getID() == AArch64::FPRRegBankID) {
347 return &AArch64::FPR16RegClass;
349 return &AArch64::FPR32RegClass;
351 return &AArch64
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H A DAArch64FastISel.cpp1 //===- AArch6464FastISel.cpp - AArch64 FastISel implementation ------------===//
9 // This file defines the AArch64-specific support for the FastISel class. Some
15 #include "AArch64.h"
368 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
388 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
389 : &AArch64::GPR32RegClass;
390 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
413 unsigned Opc = Is64Bit ? AArch64
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H A DAArch64RegisterBankInfo.cpp10 /// AArch64.
45 // (AArch64::RegBanks) is unique in the compiler. At some point, it
51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
53 assert(&AArch64::GPRRegBank == &RBGPR &&
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
58 assert(&AArch64::FPRRegBank == &RBFPR &&
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
63 assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");
67 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
73 assert(RBFPR.covers(*TRI.getRegClass(AArch64
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H A DAArch64SpeculationHardening.cpp25 // For AArch64, the following implementation choices are made to implement the
34 // . The AArch64 ABI doesn't guarantee X16 to be retained across any call.
58 // of the AArch64 conditional branches that do not use the flags as input
68 // implementation choices are made for AArch64:
79 // - On AArch64, CSDB instructions are inserted between the masking of the
117 #define AARCH64_SPECULATION_HARDENING_NAME "AArch64 speculation hardening pass"
221 BuildMI(MBB, MBBI, DL, TII->get(AArch64::DSB)).addImm(0xf);
222 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ISB)).addImm(0xf);
231 BuildMI(SplitEdgeBB, SplitEdgeBB.begin(), DL, TII->get(AArch64::CSELXr))
234 .addUse(AArch64
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H A DAArch64ExpandImm.cpp1 //===- AArch64ExpandImm.h - AArch64 Immediate Expansion -------------------===//
13 #include "AArch64.h"
69 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
82 Insn.push_back({ AArch64::MOVKXi, Imm16,
97 Insn.push_back({ AArch64::MOVKXi, Imm16,
225 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
228 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx),
237 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
266 FirstOpc = (isNeg ? AArch64::MOVNWi : AArch64
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H A DAArch64StorePairSuppress.cpp27 #define STPSUPPRESS_PASS_NAME "AArch64 Store Pair Suppression"
85 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
113 case AArch64::STRSui:
114 case AArch64::STRDui:
115 case AArch64::STURSi:
116 case AArch64::STURDi:
H A DAArch64BranchTargets.cpp29 #define AARCH64_BRANCH_TARGETS_NAME "AArch64 Branch Targets"
65 dbgs() << "********** AArch64 Branch Targets **********\n"
128 (MBBI->getOpcode() == AArch64::PACIASP ||
129 MBBI->getOpcode() == AArch64::PACIBSP))
133 TII->get(AArch64::HINT))
H A DAArch64InstrInfo.h1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
16 #include "AArch64.h"
238 /// AArch64 supports MachineCombiner.
352 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
356 case AArch64::Bcc:
357 case AArch64::CBZW:
358 case AArch64::CBZX:
359 case AArch64::CBNZW:
360 case AArch64
380 namespace AArch64 { namespace in namespace:llvm
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H A DAArch64CleanupLocalDynamicTLSPass.cpp24 #include "AArch64.h"
34 #define TLSCLEANUP_PASS_NAME "AArch64 Local Dynamic TLS Access Clean-up"
70 case AArch64::TLSDESC_CALLSEQ:
105 TII->get(TargetOpcode::COPY), AArch64::X0)
122 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
128 .addReg(AArch64::X0);
H A DAArch64SelectionDAGInfo.cpp1 //===-- AArch64SelectionDAGInfo.cpp - AArch64 SelectionDAG Info -----------===//
75 TagSrc = DAG.getRegister(AArch64::SP, MVT::i64);
130 ZeroData ? AArch64::STZGPostIndex : AArch64::STGPostIndex, dl,
142 ZeroData ? AArch64::STZGloop : AArch64::STGloop, dl, ResTys, Ops);
H A DAArch64CallLowering.cpp157 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
260 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
365 MIB.addUse(AArch64::X21, RegState::Implicit);
366 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
404 if (!CCInfo.isAllocated(AArch64::X8)) {
405 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
406 Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
715 // tail-called on AArch64 when the OS does not support dynamic
765 return IsIndirect ? AArch64
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H A DAArch64A57FPLoadBalancing.cpp30 #include "AArch64.h"
70 case AArch64::FMULSrr:
71 case AArch64::FNMULSrr:
72 case AArch64::FMULDrr:
73 case AArch64::FNMULDrr:
83 case AArch64::FMSUBSrrr:
84 case AArch64::FMADDSrrr:
85 case AArch64::FNMSUBSrrr:
86 case AArch64::FNMADDSrrr:
87 case AArch64
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H A DAArch64CompressJumpTables.cpp1 //==-- AArch64CompressJumpTables.cpp - Compress jump tables for AArch64 --====//
14 #include "AArch64.h"
58 return "AArch64 Compress Jump Tables";
65 "AArch64 compress jump tables pass", false, false)
93 if (MI.getOpcode() != AArch64::JumpTableDest32)
130 MI.setDesc(TII->get(AArch64::JumpTableDest8));
135 MI.setDesc(TII->get(AArch64::JumpTableDest16));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64FixupKinds.h1 //===-- AArch64FixupKinds.h - AArch64 Specific Fixup Entries ----*- C++ -*-===//
15 namespace AArch64 { namespace in namespace:llvm
66 } // end namespace AArch64
H A DAArch64MachObjectWriter.cpp77 case AArch64::fixup_aarch64_add_imm12:
78 case AArch64::fixup_aarch64_ldst_imm12_scale1:
79 case AArch64::fixup_aarch64_ldst_imm12_scale2:
80 case AArch64::fixup_aarch64_ldst_imm12_scale4:
81 case AArch64::fixup_aarch64_ldst_imm12_scale8:
82 case AArch64::fixup_aarch64_ldst_imm12_scale16:
97 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
116 case AArch64::fixup_aarch64_pcrel_branch26:
117 case AArch64::fixup_aarch64_pcrel_call26:
168 // AArch64 pcre
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H A DAArch64ELFObjectWriter.cpp1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
60 if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
139 case AArch64::fixup_aarch64_pcrel_adr_imm21:
144 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
166 case AArch64::fixup_aarch64_pcrel_branch26:
168 case AArch64::fixup_aarch64_pcrel_call26:
170 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
176 case AArch64::fixup_aarch64_pcrel_branch14:
178 case AArch64::fixup_aarch64_pcrel_branch19:
205 case AArch64
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H A DAArch64MCCodeEmitter.cpp1 //=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code-=//
244 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
245 ? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
246 : MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
276 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
305 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
327 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
356 0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
375 MCFixupKind Kind = MCFixupKind(AArch64
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
89 case AArch64::MOVPRFX_ZZ:
93 case AArch64::MOVPRFX_ZPmZ_B:
94 case AArch64::MOVPRFX_ZPmZ_H:
95 case AArch64::MOVPRFX_ZPmZ_S:
96 case AArch64::MOVPRFX_ZPmZ_D:
99 Prefix.ElementSize = TSFlags & AArch64::ElementSizeMask;
100 assert(Prefix.ElementSize != AArch64::ElementSizeNone &&
105 case AArch64::MOVPRFX_ZPzZ_B:
106 case AArch64
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp1 //===- AArch64ExternalSymbolizer.cpp - Symbolizer for AArch64 ---*- C++ -*-===//
92 } else if (MI.getOpcode() == AArch64::ADRP) {
105 } else if (MI.getOpcode() == AArch64::ADDXri ||
106 MI.getOpcode() == AArch64::LDRXui ||
107 MI.getOpcode() == AArch64::LDRXl ||
108 MI.getOpcode() == AArch64::ADR) {
109 if (MI.getOpcode() == AArch64::ADDXri)
111 else if (MI.getOpcode() == AArch64::LDRXui)
113 if (MI.getOpcode() == AArch64::LDRXl) {
117 } else if (MI.getOpcode() == AArch64
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/freebsd-12-stable/contrib/llvm-project/lld/ELF/Arch/
H A DAArch64.cpp1 //===- AArch64.cpp --------------------------------------------------------===//
32 class AArch64 : public TargetInfo { class in namespace:lld::elf::__anon3773
34 AArch64();
57 AArch64::AArch64() { function in class:lld::elf::AArch64
79 RelExpr AArch64::getRelExpr(RelType type, const Symbol &s,
158 RelExpr AArch64::adjustRelaxExpr(RelType type, const uint8_t *data,
168 bool AArch64::usesOnlyLowPageBits(RelType type) const {
186 RelType AArch64::getDynRel(RelType type) const {
192 void AArch64
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DAArch64TargetParser.h1 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
9 // This file implements a target parser to recognise AArch64 hardware features
24 namespace AArch64 { namespace in namespace:llvm
76 AArch64::ArchKind::ID, \
89 {NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
135 } // namespace AArch64
/freebsd-12-stable/contrib/llvm-project/clang/lib/Basic/Targets/
H A DAArch64.cpp1 //===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
9 // This file implements AArch64 TargetInfo objects.
13 #include "AArch64.h"
52 // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
92 // AArch64 targets default to using the ARM C++ ABI.
115 llvm::AArch64::ParsedBranchProtection PBP;
116 if (!llvm::AArch64::parseBranchProtection(Spec, PBP, Err))
136 llvm::AArch64::parseCPUArch(Name) != llvm::AArch64
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