Lines Matching refs:AArch64
10 /// AArch64.
45 // (AArch64::RegBanks) is unique in the compiler. At some point, it
51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
53 assert(&AArch64::GPRRegBank == &RBGPR &&
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
58 assert(&AArch64::FPRRegBank == &RBFPR &&
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
63 assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");
67 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
73 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
75 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
80 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
155 AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
215 if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)
218 if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)
229 case AArch64::FPR8RegClassID:
230 case AArch64::FPR16RegClassID:
231 case AArch64::FPR32RegClassID:
232 case AArch64::FPR64RegClassID:
233 case AArch64::FPR128RegClassID:
234 case AArch64::FPR128_loRegClassID:
235 case AArch64::DDRegClassID:
236 case AArch64::DDDRegClassID:
237 case AArch64::DDDDRegClassID:
238 case AArch64::QQRegClassID:
239 case AArch64::QQQRegClassID:
240 case AArch64::QQQQRegClassID:
241 return getRegBank(AArch64::FPRRegBankID);
242 case AArch64::GPR32commonRegClassID:
243 case AArch64::GPR32RegClassID:
244 case AArch64::GPR32spRegClassID:
245 case AArch64::GPR32sponlyRegClassID:
246 case AArch64::GPR32argRegClassID:
247 case AArch64::GPR32allRegClassID:
248 case AArch64::GPR64commonRegClassID:
249 case AArch64::GPR64RegClassID:
250 case AArch64::GPR64spRegClassID:
251 case AArch64::GPR64sponlyRegClassID:
252 case AArch64::GPR64argRegClassID:
253 case AArch64::GPR64allRegClassID:
254 case AArch64::GPR64noipRegClassID:
255 case AArch64::GPR64common_and_GPR64noipRegClassID:
256 case AArch64::GPR64noip_and_tcGPR64RegClassID:
257 case AArch64::tcGPR64RegClassID:
258 case AArch64::WSeqPairsClassRegClassID:
259 case AArch64::XSeqPairsClassRegClassID:
260 return getRegBank(AArch64::GPRRegBankID);
261 case AArch64::CCRRegClassID:
262 return getRegBank(AArch64::CCRegBankID);
313 getCopyMapping(AArch64::GPRRegBankID, AArch64::GPRRegBankID, Size),
317 getCopyMapping(AArch64::FPRRegBankID, AArch64::FPRRegBankID, Size),
321 /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
322 getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size),
326 /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
327 getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size),
477 &AArch64::FPRRegBank;
600 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
602 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
751 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank ||
795 if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)