Lines Matching refs:AArch64
157 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
260 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
365 MIB.addUse(AArch64::X21, RegState::Implicit);
366 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
404 if (!CCInfo.isAllocated(AArch64::X8)) {
405 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
406 Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
715 // tail-called on AArch64 when the OS does not support dynamic
765 return IsIndirect ? AArch64::BLR : AArch64::BL;
768 return AArch64::TCRETURNdi;
773 return AArch64::TCRETURNriBTI;
775 return AArch64::TCRETURNri;
806 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
902 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0);
964 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1013 MIB.addDef(AArch64::X21, RegState::Implicit);
1014 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1024 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)