/freebsd-11.0-release/contrib/llvm/lib/Transforms/Vectorize/ |
H A D | LoopVectorize.cpp | 2153 static Value *ConcatenateTwoVectors(IRBuilder<> &Builder, Value *V1, argument 2155 VectorType *VecTy1 = dyn_cast<VectorType>(V1->getType()); 2173 return Builder.CreateShuffleVector(V1, V2, Mask); 2187 Value *V0 = ResList[i], *V1 = ResList[i + 1]; local 2188 assert((V0->getType() == V1->getType() || i == NumVec - 2) && 2191 TmpList.push_back(ConcatenateTwoVectors(Builder, V0, V1));
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H A D | SLPVectorizer.cpp | 2518 Value *V1 = Builder.CreateBinOp(BinOp1->getOpcode(), LHS, RHS); local 2538 propagateIRFlags(V1, OddScalars); 2540 Value *V = Builder.CreateShuffleVector(V0, V1, ShuffleMask);
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/freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | SCCP.cpp | 1001 Constant *V1 = V1State.isConstant() ? 1007 markConstant(&I, ConstantExpr::getShuffleVector(V1, V2, Mask));
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngine.cpp | 1806 llvm::APSInt V1 = Case->getLHS()->EvaluateKnownConstInt(getContext()); local 1807 assert(V1.getBitWidth() == getContext().getTypeSize(CondE->getType())); 1814 V2 = V1; 1819 DefaultSt->assumeWithinInclusiveRange(*NL, V1, V2);
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 93 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 4293 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live 7172 SDValue V1 = Op.getOperand(0); local 7182 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 7186 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2, 7191 std::swap(V1, V2); 7198 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1, 7214 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3); 7313 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 7316 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 7318 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; [all...] |
H A D | PPCFrameLowering.cpp | 34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 3171 SDValue V1 = GetPromotedInteger(N->getOperand(1)); local 3174 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask); 3272 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, local 3275 V0->getValueType(0).getScalarType(), V0, V1);
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/freebsd-11.0-release/contrib/llvm/lib/IR/ |
H A D | Verifier.cpp | 155 void WriteTs(const T1 &V1, const Ts &... Vs) { argument 156 Write(V1); 177 void CheckFailed(const Twine &Message, const T1 &V1, const Ts &... Vs) { argument 179 WriteTs(V1, Vs...);
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H A D | Core.cpp | 2771 LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef B, LLVMValueRef V1, argument 2774 return wrap(unwrap(B)->CreateShuffleVector(unwrap(V1), unwrap(V2),
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/freebsd-11.0-release/contrib/binutils/opcodes/ |
H A D | mips-opc.c | 109 #define V1 (INSN_4100 | INSN_4111 | INSN_4120) macro 669 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, 1190 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, 1207 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
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/freebsd-11.0-release/contrib/llvm/include/llvm/IR/ |
H A D | Instructions.h | 2114 ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, 2117 ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, 2122 static bool isValidOperands(const Value *V1, const Value *V2,
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/freebsd-11.0-release/contrib/llvm/lib/Transforms/Utils/ |
H A D | SimplifyLibCalls.cpp | 1043 Value *V1 = valueHasFloatPrecision(CI->getArgOperand(0)); 1044 if (V1 == nullptr) 1057 Value *V = EmitBinaryFloatFnCall(V1, V2, Callee->getName(), B,
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/freebsd-11.0-release/contrib/llvm/include/llvm-c/ |
H A D | Core.h | 2762 LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef, LLVMValueRef V1,
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 508 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
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/freebsd-11.0-release/contrib/expat/lib/ |
H A D | xmlparse.c | 2030 /* V1 is used to string-ize the version number. However, it would 2032 substituted before being passed to V1. CPP is defined to expand 2034 the version macros, then CPP will expand the resulting V1() macro 2038 #define V1(a,b,c) XML_L(#a)XML_L(".")XML_L(#b)XML_L(".")XML_L(#c) macro 2039 #define V2(a,b,c) XML_L("expat_")V1(a,b,c) 2043 #undef V1 macro
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 89 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/CodeGen/ |
H A D | CGExprScalar.cpp | 1039 Value* V1 = CGF.EmitScalarExpr(E->getExpr(0)); local 1053 return Builder.CreateShuffleVector(V1, V2, SV, "shuffle");
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 451 const Value *V1 = PN->getIncomingValueForBlock(Pred); local 460 if (V1 != V2) return false;
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2055 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2057 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
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/freebsd-11.0-release/contrib/binutils/gas/config/ |
H A D | tc-arm.c | 14535 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 15056 /* V1 instructions with no Thumb analogue prior to V6T2. */ 15074 /* V1 instructions with no Thumb analogue at all. */ 15411 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 15912 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
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