/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86AsmPrinter.cpp | 50 Subtarget = &MF.getSubtarget<X86Subtarget>(); 56 if (Subtarget->isTargetCOFF()) { 414 if (Subtarget->isPICStyleRIPRel()) 564 if (Subtarget->isTargetKnownWindowsMSVC()) {
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H A D | X86MCInstLower.cpp | 400 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { argument 401 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 542 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); local 543 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 545 OutMI.setOpcode(getRetOpcode(Subtarget)); 841 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); 845 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(), 931 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); 981 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(), 1212 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); [all...] |
H A D | X86ISelDAGToDAG.cpp | 154 const X86Subtarget *Subtarget; member in class:__anon3082::final 170 Subtarget = &MF.getSubtarget<X86Subtarget>(); 383 return Subtarget->getInstrInfo(); 544 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) || 547 (Subtarget->is64Bit() || 652 if (Subtarget->isTargetCygMing()) { 691 if (Subtarget->is64Bit()) { 717 Subtarget->isTargetLinux()) 744 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP && 796 if (!Subtarget 1844 getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG, SDLoc dl, enum AtomicOpc &Op, MVT NVT, SDValue Val, const X86Subtarget *Subtarget) argument [all...] |
H A D | X86InstrInfo.cpp | 109 Subtarget(STI), RI(STI.getTargetTriple()) { 2051 if (!Subtarget.is64Bit()) 2626 if (Subtarget.is64Bit()) { 2680 if (Subtarget.is64Bit()) 2750 bool is64Bit = Subtarget.is64Bit(); 4108 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr; 4199 if (!Subtarget.hasCMov()) 4249 const X86Subtarget &Subtarget) { 4256 bool HasAVX = Subtarget.hasAVX(); 4257 bool HasAVX512 = Subtarget 4248 CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget) argument 4332 copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg, const X86Subtarget &Subtarget) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetMachine.cpp | 178 // Subtarget constructor below it. 188 Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) { 194 unsigned RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3,
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H A D | PPCInstrInfo.cpp | 69 Subtarget(STI), RI(STI.getTargetMachine()) {} 170 unsigned Directive = Subtarget.getDarwinDirective(); 236 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive) 424 unsigned Directive = Subtarget.getDarwinDirective(); 449 bool isPPC64 = Subtarget.isPPC64(); 646 bool isPPC64 = Subtarget.isPPC64(); 687 if (!Subtarget.hasISEL()) 730 assert(Subtarget.hasISEL() && 1022 assert(Subtarget.isDarwin() && 1138 assert(Subtarget [all...] |
H A D | PPCInstrInfo.h | 68 PPCSubtarget &Subtarget; member in class:llvm::PPCInstrInfo
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/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 133 const SystemZSubtarget *Subtarget; member in class:__anon3014::SystemZDAGToDAGISel 145 return Subtarget->getInstrInfo(); 336 Subtarget = &MF.getSubtarget<SystemZSubtarget>(); 948 if (Subtarget->hasHighWord()) 961 if (Subtarget->hasMiscellaneousExtensions()) 964 if (VT == MVT::i32 && Subtarget->hasHighWord()) { 1017 if (Subtarget->hasMiscellaneousExtensions())
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H A D | SystemZISelLowering.cpp | 86 : TargetLowering(TM), Subtarget(STI) { 90 if (Subtarget.hasHighWord()) 95 if (Subtarget.hasVector()) { 104 if (Subtarget.hasVector()) { 114 computeRegisterProperties(Subtarget.getRegisterInfo()); 180 if (Subtarget.hasPopulationCount()) 198 if (!Subtarget.hasFPExtension()) 221 if (!Subtarget.hasFPExtension()) { 340 if (Subtarget.hasVector()) { 359 if (Subtarget [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64LoadStoreOptimizer.cpp | 89 const AArch64Subtarget *Subtarget; member in struct:__anon2700::AArch64LoadStoreOpt 672 if (!Subtarget->isLittleEndian()) 698 if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) { 882 if (!Subtarget->isLittleEndian()) 1788 bool ProfitableArch = Subtarget->isCortexA57(); 1793 return ProfitableArch && !Subtarget->requiresStrictAlign(); 1797 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget()); 1798 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo()); 1799 TRI = Subtarget->getRegisterInfo();
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H A D | AArch64ISelLowering.cpp | 67 : TargetLowering(TM), Subtarget(&STI) { 80 if (Subtarget->hasFPARMv8()) { 87 if (Subtarget->hasNEON()) { 109 computeRegisterProperties(Subtarget->getRegisterInfo()); 407 if (Subtarget->hasPerfMon()) 410 if (Subtarget->isTargetMachO()) { 423 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) { 496 if (Subtarget->supportsAddressTopByteIgnored()) 527 if (Subtarget->hasNEON()) { 627 if (Subtarget 7366 performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 7417 performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 7522 performIntToFpCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 7564 performFpToIntCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 7628 performFDivCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 7801 performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 8378 performIntrinsicCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 8592 split16BStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 8773 performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 8920 performAcrossLaneMinMaxReductionCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 9019 performAcrossLaneAddReductionCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument [all...] |
H A D | AArch64InstrInfo.h | 38 const AArch64Subtarget &Subtarget; member in class:llvm::AArch64InstrInfo
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H A D | AArch64FastISel.cpp | 105 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can 107 const AArch64Subtarget *Subtarget; member in class:__anon2694::final 251 Subtarget = 309 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS; 375 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) { 418 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO()) 421 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM); 2828 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8()) 2832 (!Subtarget->hasNEON() || !Subtarget [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 95 : TargetLowering(TM), Subtarget(&STI) { 96 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; 107 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); 114 computeRegisterProperties(Subtarget->getRegisterInfo()); 650 Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 378 return Subtarget; 477 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 479 const ARMSubtarget *Subtarget; member in class:llvm::ARMTargetLowering 518 const ARMSubtarget *Subtarget) const;
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 84 : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr) {} 570 const MCInstrInfo &MCII = *Subtarget->getInstrInfo(); 588 MCII, *Subtarget, OutStreamer->getContext(), MCB, nullptr);
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H A D | HexagonISelLowering.h | 99 const HexagonSubtarget &Subtarget; member in class:llvm::HexagonTargetLowering
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 74 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can 77 const MipsSubtarget *Subtarget; member in class:__anon2932::final 191 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()), 192 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) { 195 bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32(); 199 UnsupportedFPMode = Subtarget->isFP64bit(); 1186 if (ArgSize < 8 && !Subtarget->isLittle()) 1347 if (Subtarget [all...] |
H A D | MipsInstrInfo.cpp | 35 Subtarget(STI), UncondBrOpc(UncondBr) {}
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUTargetMachine.cpp | 97 TLOF(createTLOF(getTargetTriple())), Subtarget(TT, CPU, FS, *this),
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H A D | AMDGPUISelLowering.h | 29 const AMDGPUSubtarget *Subtarget; member in class:llvm::AMDGPUTargetLowering
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H A D | AMDGPUInstrInfo.cpp | 326 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any 332 return getMCOpcodeGen(Opcode, (enum Subtarget)Gen);
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/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetMachine.cpp | 98 Subtarget(TT, CPU, FS, *this) {
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.h | 55 const SparcSubtarget *Subtarget; member in class:llvm::SparcTargetLowering
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/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 73 const XCoreSubtarget &Subtarget) 74 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) { 80 computeRegisterProperties(Subtarget.getRegisterInfo()); 816 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 862 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 1556 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 72 XCoreTargetLowering(const TargetMachine &TM, const XCoreSubtarget &Subtarget) argument
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