1234353Sdim//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the Mips implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14249423Sdim#include "MipsInstrInfo.h" 15249423Sdim#include "InstPrinter/MipsInstPrinter.h" 16239462Sdim#include "MipsAnalyzeImmediate.h" 17249423Sdim#include "MipsMachineFunction.h" 18280031Sdim#include "MipsSubtarget.h" 19249423Sdim#include "llvm/ADT/STLExtras.h" 20193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 21193399Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 22198090Srdivacky#include "llvm/Support/ErrorHandling.h" 23226633Sdim#include "llvm/Support/TargetRegistry.h" 24224145Sdim 25276479Sdimusing namespace llvm; 26276479Sdim 27261991Sdim#define GET_INSTRINFO_CTOR_DTOR 28193323Sed#include "MipsGenInstrInfo.inc" 29193323Sed 30261991Sdim// Pin the vtable to this file. 31261991Sdimvoid MipsInstrInfo::anchor() {} 32261991Sdim 33276479SdimMipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr) 34276479Sdim : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), 35276479Sdim Subtarget(STI), UncondBrOpc(UncondBr) {} 36193323Sed 37276479Sdimconst MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) { 38276479Sdim if (STI.inMips16Mode()) 39276479Sdim return llvm::createMips16InstrInfo(STI); 40239462Sdim 41276479Sdim return llvm::createMipsSEInstrInfo(STI); 42224145Sdim} 43224145Sdim 44239462Sdimbool MipsInstrInfo::isZeroImm(const MachineOperand &op) const { 45193323Sed return op.isImm() && op.getImm() == 0; 46193323Sed} 47193323Sed 48193323Sed/// insertNoop - If data hazard condition is found insert the target nop 49193323Sed/// instruction. 50193323Sedvoid MipsInstrInfo:: 51221345SdiminsertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 52193323Sed{ 53206124Srdivacky DebugLoc DL; 54193323Sed BuildMI(MBB, MI, DL, get(Mips::NOP)); 55193323Sed} 56193323Sed 57239462SdimMachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI, 58239462Sdim unsigned Flag) const { 59234353Sdim MachineFunction &MF = *MBB.getParent(); 60234353Sdim MachineFrameInfo &MFI = *MF.getFrameInfo(); 61234353Sdim unsigned Align = MFI.getObjectAlignment(FI); 62234353Sdim 63296417Sdim return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), 64296417Sdim Flag, MFI.getObjectSize(FI), Align); 65234353Sdim} 66234353Sdim 67193323Sed//===----------------------------------------------------------------------===// 68193323Sed// Branch Analysis 69193323Sed//===----------------------------------------------------------------------===// 70193323Sed 71239462Sdimvoid MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 72239462Sdim MachineBasicBlock *&BB, 73239462Sdim SmallVectorImpl<MachineOperand> &Cond) const { 74261991Sdim assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 75221345Sdim int NumOp = Inst->getNumExplicitOperands(); 76234353Sdim 77221345Sdim // for both int and fp branches, the last explicit operand is the 78221345Sdim // MBB. 79221345Sdim BB = Inst->getOperand(NumOp-1).getMBB(); 80221345Sdim Cond.push_back(MachineOperand::CreateImm(Opc)); 81221345Sdim 82221345Sdim for (int i=0; i<NumOp-1; i++) 83221345Sdim Cond.push_back(Inst->getOperand(i)); 84193323Sed} 85193323Sed 86221345Sdimbool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 87193323Sed MachineBasicBlock *&TBB, 88193323Sed MachineBasicBlock *&FBB, 89193323Sed SmallVectorImpl<MachineOperand> &Cond, 90249423Sdim bool AllowModify) const { 91249423Sdim SmallVector<MachineInstr*, 2> BranchInstrs; 92249423Sdim BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); 93243830Sdim 94249423Sdim return (BT == BT_None) || (BT == BT_Indirect); 95234353Sdim} 96234353Sdim 97276479Sdimvoid 98276479SdimMipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 99288943Sdim DebugLoc DL, ArrayRef<MachineOperand> Cond) const { 100221345Sdim unsigned Opc = Cond[0].getImm(); 101224145Sdim const MCInstrDesc &MCID = get(Opc); 102224145Sdim MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); 103193323Sed 104243830Sdim for (unsigned i = 1; i < Cond.size(); ++i) { 105243830Sdim if (Cond[i].isReg()) 106243830Sdim MIB.addReg(Cond[i].getReg()); 107243830Sdim else if (Cond[i].isImm()) 108243830Sdim MIB.addImm(Cond[i].getImm()); 109243830Sdim else 110243830Sdim assert(true && "Cannot copy operand"); 111243830Sdim } 112221345Sdim MIB.addMBB(TBB); 113193323Sed} 114193323Sed 115276479Sdimunsigned MipsInstrInfo::InsertBranch( 116276479Sdim MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, 117288943Sdim ArrayRef<MachineOperand> Cond, DebugLoc DL) const { 118193323Sed // Shouldn't be a fall through. 119193323Sed assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 120193323Sed 121221345Sdim // # of condition operands: 122221345Sdim // Unconditional branches: 0 123221345Sdim // Floating point branches: 1 (opc) 124221345Sdim // Int BranchZero: 2 (opc, reg) 125221345Sdim // Int Branch: 3 (opc, reg0, reg1) 126221345Sdim assert((Cond.size() <= 3) && 127221345Sdim "# of Mips branch conditions must be <= 3!"); 128193323Sed 129221345Sdim // Two-way Conditional branch. 130221345Sdim if (FBB) { 131221345Sdim BuildCondBr(MBB, TBB, DL, Cond); 132234353Sdim BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); 133221345Sdim return 2; 134193323Sed } 135193323Sed 136221345Sdim // One way branch. 137221345Sdim // Unconditional branch. 138221345Sdim if (Cond.empty()) 139234353Sdim BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); 140221345Sdim else // Conditional branch. 141221345Sdim BuildCondBr(MBB, TBB, DL, Cond); 142221345Sdim return 1; 143193323Sed} 144193323Sed 145276479Sdimunsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 146221345Sdim MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 147221345Sdim MachineBasicBlock::reverse_iterator FirstBr; 148221345Sdim unsigned removed; 149221345Sdim 150221345Sdim // Skip all the debug instructions. 151221345Sdim while (I != REnd && I->isDebugValue()) 152221345Sdim ++I; 153221345Sdim 154221345Sdim FirstBr = I; 155221345Sdim 156221345Sdim // Up to 2 branches are removed. 157221345Sdim // Note that indirect branches are not removed. 158276479Sdim for (removed = 0; I != REnd && removed < 2; ++I, ++removed) 159261991Sdim if (!getAnalyzableBrOpc(I->getOpcode())) 160221345Sdim break; 161221345Sdim 162221345Sdim MBB.erase(I.base(), FirstBr.base()); 163221345Sdim 164221345Sdim return removed; 165193323Sed} 166193323Sed 167221345Sdim/// ReverseBranchCondition - Return the inverse opcode of the 168193323Sed/// specified Branch instruction. 169276479Sdimbool MipsInstrInfo::ReverseBranchCondition( 170276479Sdim SmallVectorImpl<MachineOperand> &Cond) const { 171221345Sdim assert( (Cond.size() && Cond.size() <= 3) && 172193323Sed "Invalid Mips branch condition!"); 173261991Sdim Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); 174193323Sed return false; 175193323Sed} 176193399Sed 177276479SdimMipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch( 178276479Sdim MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 179276479Sdim SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, 180276479Sdim SmallVectorImpl<MachineInstr *> &BranchInstrs) const { 181249423Sdim 182249423Sdim MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 183249423Sdim 184249423Sdim // Skip all the debug instructions. 185249423Sdim while (I != REnd && I->isDebugValue()) 186249423Sdim ++I; 187249423Sdim 188249423Sdim if (I == REnd || !isUnpredicatedTerminator(&*I)) { 189249423Sdim // This block ends with no branches (it just falls through to its succ). 190249423Sdim // Leave TBB/FBB null. 191276479Sdim TBB = FBB = nullptr; 192249423Sdim return BT_NoBranch; 193249423Sdim } 194249423Sdim 195249423Sdim MachineInstr *LastInst = &*I; 196249423Sdim unsigned LastOpc = LastInst->getOpcode(); 197249423Sdim BranchInstrs.push_back(LastInst); 198249423Sdim 199249423Sdim // Not an analyzable branch (e.g., indirect jump). 200261991Sdim if (!getAnalyzableBrOpc(LastOpc)) 201249423Sdim return LastInst->isIndirectBranch() ? BT_Indirect : BT_None; 202249423Sdim 203249423Sdim // Get the second to last instruction in the block. 204249423Sdim unsigned SecondLastOpc = 0; 205276479Sdim MachineInstr *SecondLastInst = nullptr; 206249423Sdim 207249423Sdim if (++I != REnd) { 208249423Sdim SecondLastInst = &*I; 209261991Sdim SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode()); 210249423Sdim 211249423Sdim // Not an analyzable branch (must be an indirect jump). 212249423Sdim if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc) 213249423Sdim return BT_None; 214249423Sdim } 215249423Sdim 216249423Sdim // If there is only one terminator instruction, process it. 217249423Sdim if (!SecondLastOpc) { 218261991Sdim // Unconditional branch. 219249423Sdim if (LastOpc == UncondBrOpc) { 220249423Sdim TBB = LastInst->getOperand(0).getMBB(); 221249423Sdim return BT_Uncond; 222249423Sdim } 223249423Sdim 224249423Sdim // Conditional branch 225249423Sdim AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); 226249423Sdim return BT_Cond; 227249423Sdim } 228249423Sdim 229249423Sdim // If we reached here, there are two branches. 230249423Sdim // If there are three terminators, we don't know what sort of block this is. 231249423Sdim if (++I != REnd && isUnpredicatedTerminator(&*I)) 232249423Sdim return BT_None; 233249423Sdim 234249423Sdim BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst); 235249423Sdim 236249423Sdim // If second to last instruction is an unconditional branch, 237249423Sdim // analyze it and remove the last instruction. 238249423Sdim if (SecondLastOpc == UncondBrOpc) { 239249423Sdim // Return if the last instruction cannot be removed. 240249423Sdim if (!AllowModify) 241249423Sdim return BT_None; 242249423Sdim 243249423Sdim TBB = SecondLastInst->getOperand(0).getMBB(); 244249423Sdim LastInst->eraseFromParent(); 245249423Sdim BranchInstrs.pop_back(); 246249423Sdim return BT_Uncond; 247249423Sdim } 248249423Sdim 249249423Sdim // Conditional branch followed by an unconditional branch. 250249423Sdim // The last one must be unconditional. 251249423Sdim if (LastOpc != UncondBrOpc) 252249423Sdim return BT_None; 253249423Sdim 254249423Sdim AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); 255249423Sdim FBB = LastInst->getOperand(0).getMBB(); 256249423Sdim 257249423Sdim return BT_CondUncond; 258249423Sdim} 259249423Sdim 260239462Sdim/// Return the number of bytes of code the specified instruction may be. 261239462Sdimunsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 262239462Sdim switch (MI->getOpcode()) { 263239462Sdim default: 264239462Sdim return MI->getDesc().getSize(); 265239462Sdim case TargetOpcode::INLINEASM: { // Inline Asm: Variable size. 266239462Sdim const MachineFunction *MF = MI->getParent()->getParent(); 267239462Sdim const char *AsmStr = MI->getOperand(0).getSymbolName(); 268239462Sdim return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 269239462Sdim } 270261991Sdim case Mips::CONSTPOOL_ENTRY: 271261991Sdim // If this machine instr is a constant pool entry, its size is recorded as 272261991Sdim // operand #2. 273261991Sdim return MI->getOperand(2).getImm(); 274239462Sdim } 275239462Sdim} 276261991Sdim 277261991SdimMachineInstrBuilder 278261991SdimMipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, 279261991Sdim MachineBasicBlock::iterator I) const { 280261991Sdim MachineInstrBuilder MIB; 281261991Sdim MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); 282261991Sdim 283261991Sdim for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) 284261991Sdim MIB.addOperand(I->getOperand(J)); 285261991Sdim 286261991Sdim MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); 287261991Sdim return MIB; 288261991Sdim} 289