1234353Sdim//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the XCoreTargetLowering class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "XCoreISelLowering.h" 15249423Sdim#include "XCore.h" 16193323Sed#include "XCoreMachineFunctionInfo.h" 17249423Sdim#include "XCoreSubtarget.h" 18249423Sdim#include "XCoreTargetMachine.h" 19198090Srdivacky#include "XCoreTargetObjectFile.h" 20193323Sed#include "llvm/CodeGen/CallingConvLower.h" 21193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 22193323Sed#include "llvm/CodeGen/MachineFunction.h" 23193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 24204642Srdivacky#include "llvm/CodeGen/MachineJumpTableInfo.h" 25193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 26193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 27193323Sed#include "llvm/CodeGen/ValueTypes.h" 28249423Sdim#include "llvm/IR/CallingConv.h" 29276479Sdim#include "llvm/IR/Constants.h" 30249423Sdim#include "llvm/IR/DerivedTypes.h" 31249423Sdim#include "llvm/IR/Function.h" 32249423Sdim#include "llvm/IR/GlobalAlias.h" 33249423Sdim#include "llvm/IR/GlobalVariable.h" 34249423Sdim#include "llvm/IR/Intrinsics.h" 35193323Sed#include "llvm/Support/Debug.h" 36198090Srdivacky#include "llvm/Support/ErrorHandling.h" 37198090Srdivacky#include "llvm/Support/raw_ostream.h" 38251662Sdim#include <algorithm> 39251662Sdim 40193323Sedusing namespace llvm; 41193323Sed 42276479Sdim#define DEBUG_TYPE "xcore-lower" 43276479Sdim 44193323Sedconst char *XCoreTargetLowering:: 45219077SdimgetTargetNodeName(unsigned Opcode) const 46193323Sed{ 47288943Sdim switch ((XCoreISD::NodeType)Opcode) 48193323Sed { 49288943Sdim case XCoreISD::FIRST_NUMBER : break; 50193323Sed case XCoreISD::BL : return "XCoreISD::BL"; 51193323Sed case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper"; 52193323Sed case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper"; 53193323Sed case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper"; 54276479Sdim case XCoreISD::LDWSP : return "XCoreISD::LDWSP"; 55193323Sed case XCoreISD::STWSP : return "XCoreISD::STWSP"; 56193323Sed case XCoreISD::RETSP : return "XCoreISD::RETSP"; 57198090Srdivacky case XCoreISD::LADD : return "XCoreISD::LADD"; 58198090Srdivacky case XCoreISD::LSUB : return "XCoreISD::LSUB"; 59204961Srdivacky case XCoreISD::LMUL : return "XCoreISD::LMUL"; 60204961Srdivacky case XCoreISD::MACCU : return "XCoreISD::MACCU"; 61204961Srdivacky case XCoreISD::MACCS : return "XCoreISD::MACCS"; 62249423Sdim case XCoreISD::CRC8 : return "XCoreISD::CRC8"; 63204642Srdivacky case XCoreISD::BR_JT : return "XCoreISD::BR_JT"; 64204642Srdivacky case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32"; 65276479Sdim case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET"; 66276479Sdim case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN"; 67261991Sdim case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER"; 68193323Sed } 69288943Sdim return nullptr; 70193323Sed} 71193323Sed 72288943SdimXCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM, 73288943Sdim const XCoreSubtarget &Subtarget) 74288943Sdim : TargetLowering(TM), TM(TM), Subtarget(Subtarget) { 75193323Sed 76193323Sed // Set up the register classes. 77239462Sdim addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 78193323Sed 79193323Sed // Compute derived properties from the register classes 80288943Sdim computeRegisterProperties(Subtarget.getRegisterInfo()); 81193323Sed 82193323Sed setStackPointerRegisterToSaveRestore(XCore::SP); 83193323Sed 84261991Sdim setSchedulingPreference(Sched::Source); 85193323Sed 86193323Sed // Use i32 for setcc operations results (slt, sgt, ...). 87193323Sed setBooleanContents(ZeroOrOneBooleanContent); 88226633Sdim setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 89193323Sed 90193323Sed // XCore does not have the NodeTypes below. 91249423Sdim setOperationAction(ISD::BR_CC, MVT::i32, Expand); 92276479Sdim setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 93193323Sed setOperationAction(ISD::ADDC, MVT::i32, Expand); 94193323Sed setOperationAction(ISD::ADDE, MVT::i32, Expand); 95193323Sed setOperationAction(ISD::SUBC, MVT::i32, Expand); 96193323Sed setOperationAction(ISD::SUBE, MVT::i32, Expand); 97193323Sed 98193323Sed // 64bit 99198090Srdivacky setOperationAction(ISD::ADD, MVT::i64, Custom); 100198090Srdivacky setOperationAction(ISD::SUB, MVT::i64, Custom); 101204961Srdivacky setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 102204961Srdivacky setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 103193323Sed setOperationAction(ISD::MULHS, MVT::i32, Expand); 104193323Sed setOperationAction(ISD::MULHU, MVT::i32, Expand); 105193323Sed setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 106193323Sed setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 107193323Sed setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 108219077Sdim 109193323Sed // Bit Manipulation 110193323Sed setOperationAction(ISD::CTPOP, MVT::i32, Expand); 111193323Sed setOperationAction(ISD::ROTL , MVT::i32, Expand); 112193323Sed setOperationAction(ISD::ROTR , MVT::i32, Expand); 113234353Sdim setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 114234353Sdim setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 115219077Sdim 116193323Sed setOperationAction(ISD::TRAP, MVT::Other, Legal); 117219077Sdim 118204642Srdivacky // Jump tables. 119204642Srdivacky setOperationAction(ISD::BR_JT, MVT::Other, Custom); 120193323Sed 121193323Sed setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 122199511Srdivacky setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); 123199511Srdivacky 124193323Sed // Conversion of i64 -> double produces constantpool nodes 125193323Sed setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 126193323Sed 127193323Sed // Loads 128280031Sdim for (MVT VT : MVT::integer_valuetypes()) { 129280031Sdim setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 130280031Sdim setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 131280031Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 132193323Sed 133280031Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 134280031Sdim setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); 135280031Sdim } 136198090Srdivacky 137198090Srdivacky // Custom expand misaligned loads / stores. 138198090Srdivacky setOperationAction(ISD::LOAD, MVT::i32, Custom); 139198090Srdivacky setOperationAction(ISD::STORE, MVT::i32, Custom); 140198090Srdivacky 141193323Sed // Varargs 142193323Sed setOperationAction(ISD::VAEND, MVT::Other, Expand); 143193323Sed setOperationAction(ISD::VACOPY, MVT::Other, Expand); 144193323Sed setOperationAction(ISD::VAARG, MVT::Other, Custom); 145193323Sed setOperationAction(ISD::VASTART, MVT::Other, Custom); 146219077Sdim 147193323Sed // Dynamic stack 148193323Sed setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 149193323Sed setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 150193323Sed setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 151198090Srdivacky 152261991Sdim // Exception handling 153276479Sdim setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 154276479Sdim setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 155261991Sdim 156261991Sdim // Atomic operations 157276479Sdim // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic. 158276479Sdim // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP. 159276479Sdim setInsertFencesForAtomic(true); 160261991Sdim setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 161276479Sdim setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 162276479Sdim setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 163261991Sdim 164218893Sdim // TRAMPOLINE is custom lowered. 165226633Sdim setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 166226633Sdim setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 167218893Sdim 168249423Sdim // We want to custom lower some of our intrinsics. 169249423Sdim setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 170218893Sdim 171249423Sdim MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4; 172249423Sdim MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize 173249423Sdim = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2; 174249423Sdim 175198090Srdivacky // We have target-specific dag combine patterns for the following nodes: 176198090Srdivacky setTargetDAGCombine(ISD::STORE); 177204961Srdivacky setTargetDAGCombine(ISD::ADD); 178276479Sdim setTargetDAGCombine(ISD::INTRINSIC_VOID); 179276479Sdim setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 180223017Sdim 181223017Sdim setMinFunctionAlignment(1); 182276479Sdim setPrefFunctionAlignment(2); 183193323Sed} 184193323Sed 185261991Sdimbool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 186261991Sdim if (Val.getOpcode() != ISD::LOAD) 187261991Sdim return false; 188261991Sdim 189261991Sdim EVT VT1 = Val.getValueType(); 190261991Sdim if (!VT1.isSimple() || !VT1.isInteger() || 191261991Sdim !VT2.isSimple() || !VT2.isInteger()) 192261991Sdim return false; 193261991Sdim 194261991Sdim switch (VT1.getSimpleVT().SimpleTy) { 195261991Sdim default: break; 196261991Sdim case MVT::i8: 197261991Sdim return true; 198261991Sdim } 199261991Sdim 200261991Sdim return false; 201261991Sdim} 202261991Sdim 203193323SedSDValue XCoreTargetLowering:: 204207618SrdivackyLowerOperation(SDValue Op, SelectionDAG &DAG) const { 205219077Sdim switch (Op.getOpcode()) 206193323Sed { 207276479Sdim case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 208249423Sdim case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 209249423Sdim case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 210249423Sdim case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 211249423Sdim case ISD::BR_JT: return LowerBR_JT(Op, DAG); 212249423Sdim case ISD::LOAD: return LowerLOAD(Op, DAG); 213249423Sdim case ISD::STORE: return LowerSTORE(Op, DAG); 214249423Sdim case ISD::VAARG: return LowerVAARG(Op, DAG); 215249423Sdim case ISD::VASTART: return LowerVASTART(Op, DAG); 216249423Sdim case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG); 217249423Sdim case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG); 218193323Sed // FIXME: Remove these when LegalizeDAGTypes lands. 219193323Sed case ISD::ADD: 220249423Sdim case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 221249423Sdim case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 222276479Sdim case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 223276479Sdim case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 224249423Sdim case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 225249423Sdim case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 226249423Sdim case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 227261991Sdim case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 228276479Sdim case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG); 229276479Sdim case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG); 230193323Sed default: 231198090Srdivacky llvm_unreachable("unimplemented operand"); 232193323Sed } 233193323Sed} 234193323Sed 235193323Sed/// ReplaceNodeResults - Replace the results of node with an illegal result 236193323Sed/// type with new values built out of custom code. 237193323Sedvoid XCoreTargetLowering::ReplaceNodeResults(SDNode *N, 238193323Sed SmallVectorImpl<SDValue>&Results, 239207618Srdivacky SelectionDAG &DAG) const { 240193323Sed switch (N->getOpcode()) { 241193323Sed default: 242198090Srdivacky llvm_unreachable("Don't know how to custom expand this!"); 243193323Sed case ISD::ADD: 244193323Sed case ISD::SUB: 245193323Sed Results.push_back(ExpandADDSUB(N, DAG)); 246193323Sed return; 247193323Sed } 248193323Sed} 249193323Sed 250193323Sed//===----------------------------------------------------------------------===// 251193323Sed// Misc Lower Operation implementation 252193323Sed//===----------------------------------------------------------------------===// 253193323Sed 254276479SdimSDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA, 255276479Sdim const GlobalValue *GV, 256276479Sdim SelectionDAG &DAG) const { 257193323Sed // FIXME there is no actual debug info here 258261991Sdim SDLoc dl(GA); 259276479Sdim 260276479Sdim if (GV->getType()->getElementType()->isFunctionTy()) 261276479Sdim return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 262276479Sdim 263276479Sdim const auto *GVar = dyn_cast<GlobalVariable>(GV); 264276479Sdim if ((GV->hasSection() && StringRef(GV->getSection()).startswith(".cp.")) || 265276479Sdim (GVar && GVar->isConstant() && GV->hasLocalLinkage())) 266276479Sdim return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 267276479Sdim 268276479Sdim return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 269193323Sed} 270193323Sed 271276479Sdimstatic bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) { 272276479Sdim if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small) 273276479Sdim return true; 274276479Sdim 275276479Sdim Type *ObjType = GV->getType()->getPointerElementType(); 276276479Sdim if (!ObjType->isSized()) 277276479Sdim return false; 278276479Sdim 279288943Sdim auto &DL = GV->getParent()->getDataLayout(); 280288943Sdim unsigned ObjSize = DL.getTypeAllocSize(ObjType); 281276479Sdim return ObjSize < CodeModelLargeSize && ObjSize != 0; 282276479Sdim} 283276479Sdim 284193323SedSDValue XCoreTargetLowering:: 285207618SrdivackyLowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const 286193323Sed{ 287251662Sdim const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); 288251662Sdim const GlobalValue *GV = GN->getGlobal(); 289276479Sdim SDLoc DL(GN); 290251662Sdim int64_t Offset = GN->getOffset(); 291276479Sdim if (IsSmallObject(GV, *this)) { 292276479Sdim // We can only fold positive offsets that are a multiple of the word size. 293276479Sdim int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0); 294276479Sdim SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset); 295276479Sdim GA = getGlobalAddressWrapper(GA, GV, DAG); 296276479Sdim // Handle the rest of the offset. 297276479Sdim if (Offset != FoldedOffset) { 298288943Sdim SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL, MVT::i32); 299276479Sdim GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); 300276479Sdim } 301276479Sdim return GA; 302276479Sdim } else { 303276479Sdim // Ideally we would not fold in offset with an index <= 11. 304276479Sdim Type *Ty = Type::getInt8PtrTy(*DAG.getContext()); 305276479Sdim Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty); 306276479Sdim Ty = Type::getInt32Ty(*DAG.getContext()); 307276479Sdim Constant *Idx = ConstantInt::get(Ty, Offset); 308288943Sdim Constant *GAI = ConstantExpr::getGetElementPtr( 309288943Sdim Type::getInt8Ty(*DAG.getContext()), GA, Idx); 310276479Sdim SDValue CP = DAG.getConstantPool(GAI, MVT::i32); 311288943Sdim return DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, 312288943Sdim DAG.getEntryNode(), CP, MachinePointerInfo(), false, 313288943Sdim false, false, 0); 314251662Sdim } 315193323Sed} 316193323Sed 317193323SedSDValue XCoreTargetLowering:: 318207618SrdivackyLowerBlockAddress(SDValue Op, SelectionDAG &DAG) const 319199511Srdivacky{ 320261991Sdim SDLoc DL(Op); 321288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 322207618Srdivacky const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 323288943Sdim SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT); 324199511Srdivacky 325288943Sdim return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result); 326199511Srdivacky} 327199511Srdivacky 328199511SrdivackySDValue XCoreTargetLowering:: 329207618SrdivackyLowerConstantPool(SDValue Op, SelectionDAG &DAG) const 330193323Sed{ 331193323Sed ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 332193323Sed // FIXME there isn't really debug info here 333261991Sdim SDLoc dl(CP); 334198090Srdivacky EVT PtrVT = Op.getValueType(); 335198090Srdivacky SDValue Res; 336198090Srdivacky if (CP->isMachineConstantPoolEntry()) { 337198090Srdivacky Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 338276479Sdim CP->getAlignment(), CP->getOffset()); 339193323Sed } else { 340198090Srdivacky Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 341276479Sdim CP->getAlignment(), CP->getOffset()); 342193323Sed } 343198090Srdivacky return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 344193323Sed} 345193323Sed 346205218Srdivackyunsigned XCoreTargetLowering::getJumpTableEncoding() const { 347205218Srdivacky return MachineJumpTableInfo::EK_Inline; 348205218Srdivacky} 349205218Srdivacky 350193323SedSDValue XCoreTargetLowering:: 351207618SrdivackyLowerBR_JT(SDValue Op, SelectionDAG &DAG) const 352193323Sed{ 353204642Srdivacky SDValue Chain = Op.getOperand(0); 354204642Srdivacky SDValue Table = Op.getOperand(1); 355204642Srdivacky SDValue Index = Op.getOperand(2); 356261991Sdim SDLoc dl(Op); 357204642Srdivacky JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 358204642Srdivacky unsigned JTI = JT->getIndex(); 359204642Srdivacky MachineFunction &MF = DAG.getMachineFunction(); 360204642Srdivacky const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 361204642Srdivacky SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 362204642Srdivacky 363204642Srdivacky unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size(); 364204642Srdivacky if (NumEntries <= 32) { 365204642Srdivacky return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); 366204642Srdivacky } 367204642Srdivacky assert((NumEntries >> 31) == 0); 368204642Srdivacky SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 369288943Sdim DAG.getConstant(1, dl, MVT::i32)); 370204642Srdivacky return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, 371204642Srdivacky ScaledIndex); 372193323Sed} 373193323Sed 374251662SdimSDValue XCoreTargetLowering:: 375261991SdimlowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base, 376251662Sdim int64_t Offset, SelectionDAG &DAG) const 377198090Srdivacky{ 378288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 379251662Sdim if ((Offset & 0x3) == 0) { 380288943Sdim return DAG.getLoad(PtrVT, DL, Chain, Base, MachinePointerInfo(), false, 381288943Sdim false, false, 0); 382198090Srdivacky } 383251662Sdim // Lower to pair of consecutive word aligned loads plus some bit shifting. 384251662Sdim int32_t HighOffset = RoundUpToAlignment(Offset, 4); 385251662Sdim int32_t LowOffset = HighOffset - 4; 386251662Sdim SDValue LowAddr, HighAddr; 387251662Sdim if (GlobalAddressSDNode *GASD = 388251662Sdim dyn_cast<GlobalAddressSDNode>(Base.getNode())) { 389251662Sdim LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 390251662Sdim LowOffset); 391251662Sdim HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 392251662Sdim HighOffset); 393251662Sdim } else { 394251662Sdim LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 395288943Sdim DAG.getConstant(LowOffset, DL, MVT::i32)); 396251662Sdim HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 397288943Sdim DAG.getConstant(HighOffset, DL, MVT::i32)); 398198090Srdivacky } 399288943Sdim SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32); 400288943Sdim SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32); 401251662Sdim 402288943Sdim SDValue Low = DAG.getLoad(PtrVT, DL, Chain, LowAddr, MachinePointerInfo(), 403251662Sdim false, false, false, 0); 404288943Sdim SDValue High = DAG.getLoad(PtrVT, DL, Chain, HighAddr, MachinePointerInfo(), 405251662Sdim false, false, false, 0); 406251662Sdim SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); 407251662Sdim SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); 408251662Sdim SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); 409251662Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 410251662Sdim High.getValue(1)); 411251662Sdim SDValue Ops[] = { Result, Chain }; 412276479Sdim return DAG.getMergeValues(Ops, DL); 413198090Srdivacky} 414198090Srdivacky 415251662Sdimstatic bool isWordAligned(SDValue Value, SelectionDAG &DAG) 416251662Sdim{ 417251662Sdim APInt KnownZero, KnownOne; 418276479Sdim DAG.computeKnownBits(Value, KnownZero, KnownOne); 419251662Sdim return KnownZero.countTrailingOnes() >= 2; 420251662Sdim} 421251662Sdim 422193323SedSDValue XCoreTargetLowering:: 423218893SdimLowerLOAD(SDValue Op, SelectionDAG &DAG) const { 424251662Sdim const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 425198090Srdivacky LoadSDNode *LD = cast<LoadSDNode>(Op); 426198090Srdivacky assert(LD->getExtensionType() == ISD::NON_EXTLOAD && 427198090Srdivacky "Unexpected extension type"); 428198090Srdivacky assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); 429280031Sdim if (allowsMisalignedMemoryAccesses(LD->getMemoryVT(), 430280031Sdim LD->getAddressSpace(), 431280031Sdim LD->getAlignment())) 432198090Srdivacky return SDValue(); 433218893Sdim 434288943Sdim auto &TD = DAG.getDataLayout(); 435288943Sdim unsigned ABIAlignment = TD.getABITypeAlignment( 436288943Sdim LD->getMemoryVT().getTypeForEVT(*DAG.getContext())); 437198090Srdivacky // Leave aligned load alone. 438218893Sdim if (LD->getAlignment() >= ABIAlignment) 439198090Srdivacky return SDValue(); 440218893Sdim 441198090Srdivacky SDValue Chain = LD->getChain(); 442198090Srdivacky SDValue BasePtr = LD->getBasePtr(); 443261991Sdim SDLoc DL(Op); 444219077Sdim 445251662Sdim if (!LD->isVolatile()) { 446251662Sdim const GlobalValue *GV; 447251662Sdim int64_t Offset = 0; 448251662Sdim if (DAG.isBaseWithConstantOffset(BasePtr) && 449251662Sdim isWordAligned(BasePtr->getOperand(0), DAG)) { 450251662Sdim SDValue NewBasePtr = BasePtr->getOperand(0); 451251662Sdim Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue(); 452251662Sdim return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 453251662Sdim Offset, DAG); 454198090Srdivacky } 455251662Sdim if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) && 456251662Sdim MinAlign(GV->getAlignment(), 4) == 4) { 457251662Sdim SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL, 458251662Sdim BasePtr->getValueType(0)); 459251662Sdim return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 460251662Sdim Offset, DAG); 461251662Sdim } 462198090Srdivacky } 463219077Sdim 464198090Srdivacky if (LD->getAlignment() == 2) { 465218893Sdim SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, 466218893Sdim BasePtr, LD->getPointerInfo(), MVT::i16, 467280031Sdim LD->isVolatile(), LD->isNonTemporal(), 468280031Sdim LD->isInvariant(), 2); 469218893Sdim SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 470288943Sdim DAG.getConstant(2, DL, MVT::i32)); 471218893Sdim SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, 472218893Sdim HighAddr, 473218893Sdim LD->getPointerInfo().getWithOffset(2), 474203954Srdivacky MVT::i16, LD->isVolatile(), 475280031Sdim LD->isNonTemporal(), LD->isInvariant(), 2); 476218893Sdim SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, 477288943Sdim DAG.getConstant(16, DL, MVT::i32)); 478218893Sdim SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); 479218893Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 480198090Srdivacky High.getValue(1)); 481198090Srdivacky SDValue Ops[] = { Result, Chain }; 482276479Sdim return DAG.getMergeValues(Ops, DL); 483198090Srdivacky } 484219077Sdim 485198090Srdivacky // Lower to a call to __misaligned_load(BasePtr). 486288943Sdim Type *IntPtrTy = TD.getIntPtrType(*DAG.getContext()); 487198090Srdivacky TargetLowering::ArgListTy Args; 488198090Srdivacky TargetLowering::ArgListEntry Entry; 489219077Sdim 490198090Srdivacky Entry.Ty = IntPtrTy; 491198090Srdivacky Entry.Node = BasePtr; 492198090Srdivacky Args.push_back(Entry); 493219077Sdim 494276479Sdim TargetLowering::CallLoweringInfo CLI(DAG); 495288943Sdim CLI.setDebugLoc(DL).setChain(Chain).setCallee( 496288943Sdim CallingConv::C, IntPtrTy, 497288943Sdim DAG.getExternalSymbol("__misaligned_load", 498288943Sdim getPointerTy(DAG.getDataLayout())), 499288943Sdim std::move(Args), 0); 500276479Sdim 501239462Sdim std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 502276479Sdim SDValue Ops[] = { CallResult.first, CallResult.second }; 503276479Sdim return DAG.getMergeValues(Ops, DL); 504198090Srdivacky} 505198090Srdivacky 506198090SrdivackySDValue XCoreTargetLowering:: 507207618SrdivackyLowerSTORE(SDValue Op, SelectionDAG &DAG) const 508198090Srdivacky{ 509198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(Op); 510198090Srdivacky assert(!ST->isTruncatingStore() && "Unexpected store type"); 511198090Srdivacky assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 512280031Sdim if (allowsMisalignedMemoryAccesses(ST->getMemoryVT(), 513280031Sdim ST->getAddressSpace(), 514280031Sdim ST->getAlignment())) { 515198090Srdivacky return SDValue(); 516198090Srdivacky } 517288943Sdim unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment( 518288943Sdim ST->getMemoryVT().getTypeForEVT(*DAG.getContext())); 519198090Srdivacky // Leave aligned store alone. 520198090Srdivacky if (ST->getAlignment() >= ABIAlignment) { 521198090Srdivacky return SDValue(); 522198090Srdivacky } 523198090Srdivacky SDValue Chain = ST->getChain(); 524198090Srdivacky SDValue BasePtr = ST->getBasePtr(); 525198090Srdivacky SDValue Value = ST->getValue(); 526261991Sdim SDLoc dl(Op); 527219077Sdim 528198090Srdivacky if (ST->getAlignment() == 2) { 529198090Srdivacky SDValue Low = Value; 530198090Srdivacky SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, 531288943Sdim DAG.getConstant(16, dl, MVT::i32)); 532198090Srdivacky SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, 533218893Sdim ST->getPointerInfo(), MVT::i16, 534203954Srdivacky ST->isVolatile(), ST->isNonTemporal(), 535203954Srdivacky 2); 536198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 537288943Sdim DAG.getConstant(2, dl, MVT::i32)); 538198090Srdivacky SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, 539218893Sdim ST->getPointerInfo().getWithOffset(2), 540203954Srdivacky MVT::i16, ST->isVolatile(), 541203954Srdivacky ST->isNonTemporal(), 2); 542198090Srdivacky return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); 543198090Srdivacky } 544219077Sdim 545198090Srdivacky // Lower to a call to __misaligned_store(BasePtr, Value). 546288943Sdim Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext()); 547198090Srdivacky TargetLowering::ArgListTy Args; 548198090Srdivacky TargetLowering::ArgListEntry Entry; 549219077Sdim 550198090Srdivacky Entry.Ty = IntPtrTy; 551198090Srdivacky Entry.Node = BasePtr; 552198090Srdivacky Args.push_back(Entry); 553219077Sdim 554198090Srdivacky Entry.Node = Value; 555198090Srdivacky Args.push_back(Entry); 556219077Sdim 557276479Sdim TargetLowering::CallLoweringInfo CLI(DAG); 558288943Sdim CLI.setDebugLoc(dl).setChain(Chain).setCallee( 559288943Sdim CallingConv::C, Type::getVoidTy(*DAG.getContext()), 560288943Sdim DAG.getExternalSymbol("__misaligned_store", 561288943Sdim getPointerTy(DAG.getDataLayout())), 562288943Sdim std::move(Args), 0); 563276479Sdim 564239462Sdim std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 565198090Srdivacky return CallResult.second; 566198090Srdivacky} 567198090Srdivacky 568198090SrdivackySDValue XCoreTargetLowering:: 569207618SrdivackyLowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 570204961Srdivacky{ 571204961Srdivacky assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI && 572204961Srdivacky "Unexpected operand to lower!"); 573261991Sdim SDLoc dl(Op); 574204961Srdivacky SDValue LHS = Op.getOperand(0); 575204961Srdivacky SDValue RHS = Op.getOperand(1); 576288943Sdim SDValue Zero = DAG.getConstant(0, dl, MVT::i32); 577204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 578204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, 579204961Srdivacky LHS, RHS); 580204961Srdivacky SDValue Lo(Hi.getNode(), 1); 581204961Srdivacky SDValue Ops[] = { Lo, Hi }; 582276479Sdim return DAG.getMergeValues(Ops, dl); 583204961Srdivacky} 584204961Srdivacky 585204961SrdivackySDValue XCoreTargetLowering:: 586207618SrdivackyLowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 587204961Srdivacky{ 588204961Srdivacky assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI && 589204961Srdivacky "Unexpected operand to lower!"); 590261991Sdim SDLoc dl(Op); 591204961Srdivacky SDValue LHS = Op.getOperand(0); 592204961Srdivacky SDValue RHS = Op.getOperand(1); 593288943Sdim SDValue Zero = DAG.getConstant(0, dl, MVT::i32); 594204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 595204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, 596204961Srdivacky Zero, Zero); 597204961Srdivacky SDValue Lo(Hi.getNode(), 1); 598204961Srdivacky SDValue Ops[] = { Lo, Hi }; 599276479Sdim return DAG.getMergeValues(Ops, dl); 600204961Srdivacky} 601204961Srdivacky 602204961Srdivacky/// isADDADDMUL - Return whether Op is in a form that is equivalent to 603204961Srdivacky/// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then 604204961Srdivacky/// each intermediate result in the calculation must also have a single use. 605204961Srdivacky/// If the Op is in the correct form the constituent parts are written to Mul0, 606204961Srdivacky/// Mul1, Addend0 and Addend1. 607204961Srdivackystatic bool 608204961SrdivackyisADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, 609204961Srdivacky SDValue &Addend1, bool requireIntermediatesHaveOneUse) 610204961Srdivacky{ 611204961Srdivacky if (Op.getOpcode() != ISD::ADD) 612204961Srdivacky return false; 613204961Srdivacky SDValue N0 = Op.getOperand(0); 614204961Srdivacky SDValue N1 = Op.getOperand(1); 615204961Srdivacky SDValue AddOp; 616204961Srdivacky SDValue OtherOp; 617204961Srdivacky if (N0.getOpcode() == ISD::ADD) { 618204961Srdivacky AddOp = N0; 619204961Srdivacky OtherOp = N1; 620204961Srdivacky } else if (N1.getOpcode() == ISD::ADD) { 621204961Srdivacky AddOp = N1; 622204961Srdivacky OtherOp = N0; 623204961Srdivacky } else { 624204961Srdivacky return false; 625204961Srdivacky } 626204961Srdivacky if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse()) 627204961Srdivacky return false; 628204961Srdivacky if (OtherOp.getOpcode() == ISD::MUL) { 629204961Srdivacky // add(add(a,b),mul(x,y)) 630204961Srdivacky if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse()) 631204961Srdivacky return false; 632204961Srdivacky Mul0 = OtherOp.getOperand(0); 633204961Srdivacky Mul1 = OtherOp.getOperand(1); 634204961Srdivacky Addend0 = AddOp.getOperand(0); 635204961Srdivacky Addend1 = AddOp.getOperand(1); 636204961Srdivacky return true; 637204961Srdivacky } 638204961Srdivacky if (AddOp.getOperand(0).getOpcode() == ISD::MUL) { 639204961Srdivacky // add(add(mul(x,y),a),b) 640204961Srdivacky if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse()) 641204961Srdivacky return false; 642204961Srdivacky Mul0 = AddOp.getOperand(0).getOperand(0); 643204961Srdivacky Mul1 = AddOp.getOperand(0).getOperand(1); 644204961Srdivacky Addend0 = AddOp.getOperand(1); 645204961Srdivacky Addend1 = OtherOp; 646204961Srdivacky return true; 647204961Srdivacky } 648204961Srdivacky if (AddOp.getOperand(1).getOpcode() == ISD::MUL) { 649204961Srdivacky // add(add(a,mul(x,y)),b) 650204961Srdivacky if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse()) 651204961Srdivacky return false; 652204961Srdivacky Mul0 = AddOp.getOperand(1).getOperand(0); 653204961Srdivacky Mul1 = AddOp.getOperand(1).getOperand(1); 654204961Srdivacky Addend0 = AddOp.getOperand(0); 655204961Srdivacky Addend1 = OtherOp; 656204961Srdivacky return true; 657204961Srdivacky } 658204961Srdivacky return false; 659204961Srdivacky} 660204961Srdivacky 661204961SrdivackySDValue XCoreTargetLowering:: 662207618SrdivackyTryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const 663204961Srdivacky{ 664204961Srdivacky SDValue Mul; 665204961Srdivacky SDValue Other; 666204961Srdivacky if (N->getOperand(0).getOpcode() == ISD::MUL) { 667204961Srdivacky Mul = N->getOperand(0); 668204961Srdivacky Other = N->getOperand(1); 669204961Srdivacky } else if (N->getOperand(1).getOpcode() == ISD::MUL) { 670204961Srdivacky Mul = N->getOperand(1); 671204961Srdivacky Other = N->getOperand(0); 672204961Srdivacky } else { 673204961Srdivacky return SDValue(); 674204961Srdivacky } 675261991Sdim SDLoc dl(N); 676204961Srdivacky SDValue LL, RL, AddendL, AddendH; 677204961Srdivacky LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 678288943Sdim Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32)); 679204961Srdivacky RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 680288943Sdim Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32)); 681204961Srdivacky AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 682288943Sdim Other, DAG.getConstant(0, dl, MVT::i32)); 683204961Srdivacky AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 684288943Sdim Other, DAG.getConstant(1, dl, MVT::i32)); 685204961Srdivacky APInt HighMask = APInt::getHighBitsSet(64, 32); 686204961Srdivacky unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0)); 687204961Srdivacky unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1)); 688204961Srdivacky if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && 689204961Srdivacky DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { 690204961Srdivacky // The inputs are both zero-extended. 691204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 692204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), AddendH, 693204961Srdivacky AddendL, LL, RL); 694204961Srdivacky SDValue Lo(Hi.getNode(), 1); 695204961Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 696204961Srdivacky } 697204961Srdivacky if (LHSSB > 32 && RHSSB > 32) { 698204961Srdivacky // The inputs are both sign-extended. 699204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 700204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), AddendH, 701204961Srdivacky AddendL, LL, RL); 702204961Srdivacky SDValue Lo(Hi.getNode(), 1); 703204961Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 704204961Srdivacky } 705204961Srdivacky SDValue LH, RH; 706204961Srdivacky LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 707288943Sdim Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32)); 708204961Srdivacky RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 709288943Sdim Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32)); 710204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 711204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), AddendH, 712204961Srdivacky AddendL, LL, RL); 713204961Srdivacky SDValue Lo(Hi.getNode(), 1); 714204961Srdivacky RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); 715204961Srdivacky LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); 716204961Srdivacky Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); 717204961Srdivacky Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); 718204961Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 719204961Srdivacky} 720204961Srdivacky 721204961SrdivackySDValue XCoreTargetLowering:: 722207618SrdivackyExpandADDSUB(SDNode *N, SelectionDAG &DAG) const 723193323Sed{ 724193323Sed assert(N->getValueType(0) == MVT::i64 && 725193323Sed (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 726193323Sed "Unknown operand to lower!"); 727204961Srdivacky 728204961Srdivacky if (N->getOpcode() == ISD::ADD) { 729204961Srdivacky SDValue Result = TryExpandADDWithMul(N, DAG); 730276479Sdim if (Result.getNode()) 731204961Srdivacky return Result; 732204961Srdivacky } 733204961Srdivacky 734261991Sdim SDLoc dl(N); 735219077Sdim 736193323Sed // Extract components 737193323Sed SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 738288943Sdim N->getOperand(0), 739288943Sdim DAG.getConstant(0, dl, MVT::i32)); 740193323Sed SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 741288943Sdim N->getOperand(0), 742288943Sdim DAG.getConstant(1, dl, MVT::i32)); 743193323Sed SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 744288943Sdim N->getOperand(1), 745288943Sdim DAG.getConstant(0, dl, MVT::i32)); 746193323Sed SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 747288943Sdim N->getOperand(1), 748288943Sdim DAG.getConstant(1, dl, MVT::i32)); 749219077Sdim 750193323Sed // Expand 751193323Sed unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : 752193323Sed XCoreISD::LSUB; 753288943Sdim SDValue Zero = DAG.getConstant(0, dl, MVT::i32); 754249423Sdim SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 755249423Sdim LHSL, RHSL, Zero); 756249423Sdim SDValue Carry(Lo.getNode(), 1); 757219077Sdim 758249423Sdim SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 759249423Sdim LHSH, RHSH, Carry); 760249423Sdim SDValue Ignored(Hi.getNode(), 1); 761193323Sed // Merge the pieces 762193323Sed return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 763193323Sed} 764193323Sed 765193323SedSDValue XCoreTargetLowering:: 766207618SrdivackyLowerVAARG(SDValue Op, SelectionDAG &DAG) const 767193323Sed{ 768261991Sdim // Whist llvm does not support aggregate varargs we can ignore 769261991Sdim // the possibility of the ValueType being an implicit byVal vararg. 770193323Sed SDNode *Node = Op.getNode(); 771261991Sdim EVT VT = Node->getValueType(0); // not an aggregate 772261991Sdim SDValue InChain = Node->getOperand(0); 773261991Sdim SDValue VAListPtr = Node->getOperand(1); 774261991Sdim EVT PtrVT = VAListPtr.getValueType(); 775261991Sdim const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 776261991Sdim SDLoc dl(Node); 777261991Sdim SDValue VAList = DAG.getLoad(PtrVT, dl, InChain, 778261991Sdim VAListPtr, MachinePointerInfo(SV), 779234353Sdim false, false, false, 0); 780193323Sed // Increment the pointer, VAList, to the next vararg 781261991Sdim SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList, 782288943Sdim DAG.getIntPtrConstant(VT.getSizeInBits() / 8, 783288943Sdim dl)); 784193323Sed // Store the incremented VAList to the legalized pointer 785261991Sdim InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr, 786261991Sdim MachinePointerInfo(SV), false, false, 0); 787193323Sed // Load the actual argument out of the pointer VAList 788261991Sdim return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 789234353Sdim false, false, false, 0); 790193323Sed} 791193323Sed 792193323SedSDValue XCoreTargetLowering:: 793207618SrdivackyLowerVASTART(SDValue Op, SelectionDAG &DAG) const 794193323Sed{ 795261991Sdim SDLoc dl(Op); 796193323Sed // vastart stores the address of the VarArgsFrameIndex slot into the 797193323Sed // memory location argument 798193323Sed MachineFunction &MF = DAG.getMachineFunction(); 799193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 800193323Sed SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); 801219077Sdim return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), 802218893Sdim MachinePointerInfo(), false, false, 0); 803193323Sed} 804193323Sed 805207618SrdivackySDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, 806207618Srdivacky SelectionDAG &DAG) const { 807276479Sdim // This nodes represent llvm.frameaddress on the DAG. 808276479Sdim // It takes one operand, the index of the frame address to return. 809276479Sdim // An index of zero corresponds to the current function's frame address. 810276479Sdim // An index of one to the parent's frame address, and so on. 811219077Sdim // Depths > 0 not supported yet! 812193323Sed if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 813193323Sed return SDValue(); 814219077Sdim 815193323Sed MachineFunction &MF = DAG.getMachineFunction(); 816288943Sdim const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 817276479Sdim return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), 818193323Sed RegInfo->getFrameRegister(MF), MVT::i32); 819193323Sed} 820193323Sed 821218893SdimSDValue XCoreTargetLowering:: 822276479SdimLowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { 823276479Sdim // This nodes represent llvm.returnaddress on the DAG. 824276479Sdim // It takes one operand, the index of the return address to return. 825276479Sdim // An index of zero corresponds to the current function's return address. 826276479Sdim // An index of one to the parent's return address, and so on. 827276479Sdim // Depths > 0 not supported yet! 828276479Sdim if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 829276479Sdim return SDValue(); 830276479Sdim 831276479Sdim MachineFunction &MF = DAG.getMachineFunction(); 832276479Sdim XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 833276479Sdim int FI = XFI->createLRSpillSlot(MF); 834276479Sdim SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 835288943Sdim return DAG.getLoad( 836288943Sdim getPointerTy(DAG.getDataLayout()), SDLoc(Op), DAG.getEntryNode(), FIN, 837296417Sdim MachinePointerInfo::getFixedStack(MF, FI), false, false, false, 0); 838276479Sdim} 839276479Sdim 840276479SdimSDValue XCoreTargetLowering:: 841276479SdimLowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const { 842276479Sdim // This node represents offset from frame pointer to first on-stack argument. 843276479Sdim // This is needed for correct stack adjustment during unwind. 844276479Sdim // However, we don't know the offset until after the frame has be finalised. 845276479Sdim // This is done during the XCoreFTAOElim pass. 846276479Sdim return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32); 847276479Sdim} 848276479Sdim 849276479SdimSDValue XCoreTargetLowering:: 850276479SdimLowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 851276479Sdim // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) 852276479Sdim // This node represents 'eh_return' gcc dwarf builtin, which is used to 853276479Sdim // return from exception. The general meaning is: adjust stack by OFFSET and 854276479Sdim // pass execution to HANDLER. 855276479Sdim MachineFunction &MF = DAG.getMachineFunction(); 856276479Sdim SDValue Chain = Op.getOperand(0); 857276479Sdim SDValue Offset = Op.getOperand(1); 858276479Sdim SDValue Handler = Op.getOperand(2); 859276479Sdim SDLoc dl(Op); 860276479Sdim 861276479Sdim // Absolute SP = (FP + FrameToArgs) + Offset 862288943Sdim const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 863276479Sdim SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 864276479Sdim RegInfo->getFrameRegister(MF), MVT::i32); 865276479Sdim SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl, 866276479Sdim MVT::i32); 867276479Sdim Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs); 868276479Sdim Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset); 869276479Sdim 870276479Sdim // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 871276479Sdim // which leaves 2 caller saved registers, R2 & R3 for us to use. 872276479Sdim unsigned StackReg = XCore::R2; 873276479Sdim unsigned HandlerReg = XCore::R3; 874276479Sdim 875276479Sdim SDValue OutChains[] = { 876276479Sdim DAG.getCopyToReg(Chain, dl, StackReg, Stack), 877276479Sdim DAG.getCopyToReg(Chain, dl, HandlerReg, Handler) 878276479Sdim }; 879276479Sdim 880276479Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); 881276479Sdim 882276479Sdim return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain, 883276479Sdim DAG.getRegister(StackReg, MVT::i32), 884276479Sdim DAG.getRegister(HandlerReg, MVT::i32)); 885276479Sdim 886276479Sdim} 887276479Sdim 888276479SdimSDValue XCoreTargetLowering:: 889226633SdimLowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 890226633Sdim return Op.getOperand(0); 891226633Sdim} 892226633Sdim 893226633SdimSDValue XCoreTargetLowering:: 894226633SdimLowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 895218893Sdim SDValue Chain = Op.getOperand(0); 896218893Sdim SDValue Trmp = Op.getOperand(1); // trampoline 897218893Sdim SDValue FPtr = Op.getOperand(2); // nested function 898218893Sdim SDValue Nest = Op.getOperand(3); // 'nest' parameter value 899218893Sdim 900218893Sdim const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 901218893Sdim 902218893Sdim // .align 4 903218893Sdim // LDAPF_u10 r11, nest 904218893Sdim // LDW_2rus r11, r11[0] 905218893Sdim // STWSP_ru6 r11, sp[0] 906218893Sdim // LDAPF_u10 r11, fptr 907218893Sdim // LDW_2rus r11, r11[0] 908218893Sdim // BAU_1r r11 909218893Sdim // nest: 910218893Sdim // .word nest 911218893Sdim // fptr: 912218893Sdim // .word fptr 913218893Sdim SDValue OutChains[5]; 914218893Sdim 915218893Sdim SDValue Addr = Trmp; 916218893Sdim 917261991Sdim SDLoc dl(Op); 918288943Sdim OutChains[0] = DAG.getStore(Chain, dl, 919288943Sdim DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr, 920288943Sdim MachinePointerInfo(TrmpAddr), false, false, 0); 921218893Sdim 922218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 923288943Sdim DAG.getConstant(4, dl, MVT::i32)); 924288943Sdim OutChains[1] = DAG.getStore(Chain, dl, 925288943Sdim DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr, 926288943Sdim MachinePointerInfo(TrmpAddr, 4), false, false, 0); 927218893Sdim 928218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 929288943Sdim DAG.getConstant(8, dl, MVT::i32)); 930288943Sdim OutChains[2] = DAG.getStore(Chain, dl, 931288943Sdim DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr, 932288943Sdim MachinePointerInfo(TrmpAddr, 8), false, false, 0); 933218893Sdim 934218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 935288943Sdim DAG.getConstant(12, dl, MVT::i32)); 936218893Sdim OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr, 937218893Sdim MachinePointerInfo(TrmpAddr, 12), false, false, 938218893Sdim 0); 939218893Sdim 940218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 941288943Sdim DAG.getConstant(16, dl, MVT::i32)); 942218893Sdim OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr, 943218893Sdim MachinePointerInfo(TrmpAddr, 16), false, false, 944218893Sdim 0); 945218893Sdim 946276479Sdim return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); 947218893Sdim} 948218893Sdim 949249423SdimSDValue XCoreTargetLowering:: 950249423SdimLowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 951261991Sdim SDLoc DL(Op); 952249423Sdim unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 953249423Sdim switch (IntNo) { 954249423Sdim case Intrinsic::xcore_crc8: 955249423Sdim EVT VT = Op.getValueType(); 956249423Sdim SDValue Data = 957249423Sdim DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), 958249423Sdim Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); 959249423Sdim SDValue Crc(Data.getNode(), 1); 960249423Sdim SDValue Results[] = { Crc, Data }; 961276479Sdim return DAG.getMergeValues(Results, DL); 962249423Sdim } 963249423Sdim return SDValue(); 964249423Sdim} 965249423Sdim 966261991SdimSDValue XCoreTargetLowering:: 967261991SdimLowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { 968261991Sdim SDLoc DL(Op); 969261991Sdim return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0)); 970261991Sdim} 971261991Sdim 972276479SdimSDValue XCoreTargetLowering:: 973276479SdimLowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const { 974276479Sdim AtomicSDNode *N = cast<AtomicSDNode>(Op); 975276479Sdim assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP"); 976276479Sdim assert(N->getOrdering() <= Monotonic && 977276479Sdim "setInsertFencesForAtomic(true) and yet greater than Monotonic"); 978276479Sdim if (N->getMemoryVT() == MVT::i32) { 979276479Sdim if (N->getAlignment() < 4) 980276479Sdim report_fatal_error("atomic load must be aligned"); 981288943Sdim return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op), 982288943Sdim N->getChain(), N->getBasePtr(), N->getPointerInfo(), 983288943Sdim N->isVolatile(), N->isNonTemporal(), N->isInvariant(), 984288943Sdim N->getAlignment(), N->getAAInfo(), N->getRanges()); 985276479Sdim } 986276479Sdim if (N->getMemoryVT() == MVT::i16) { 987276479Sdim if (N->getAlignment() < 2) 988276479Sdim report_fatal_error("atomic load must be aligned"); 989276479Sdim return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), 990276479Sdim N->getBasePtr(), N->getPointerInfo(), MVT::i16, 991276479Sdim N->isVolatile(), N->isNonTemporal(), 992280031Sdim N->isInvariant(), N->getAlignment(), N->getAAInfo()); 993276479Sdim } 994276479Sdim if (N->getMemoryVT() == MVT::i8) 995276479Sdim return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), 996276479Sdim N->getBasePtr(), N->getPointerInfo(), MVT::i8, 997276479Sdim N->isVolatile(), N->isNonTemporal(), 998280031Sdim N->isInvariant(), N->getAlignment(), N->getAAInfo()); 999276479Sdim return SDValue(); 1000276479Sdim} 1001276479Sdim 1002276479SdimSDValue XCoreTargetLowering:: 1003276479SdimLowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const { 1004276479Sdim AtomicSDNode *N = cast<AtomicSDNode>(Op); 1005276479Sdim assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP"); 1006276479Sdim assert(N->getOrdering() <= Monotonic && 1007276479Sdim "setInsertFencesForAtomic(true) and yet greater than Monotonic"); 1008276479Sdim if (N->getMemoryVT() == MVT::i32) { 1009276479Sdim if (N->getAlignment() < 4) 1010276479Sdim report_fatal_error("atomic store must be aligned"); 1011276479Sdim return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), 1012276479Sdim N->getBasePtr(), N->getPointerInfo(), 1013276479Sdim N->isVolatile(), N->isNonTemporal(), 1014280031Sdim N->getAlignment(), N->getAAInfo()); 1015276479Sdim } 1016276479Sdim if (N->getMemoryVT() == MVT::i16) { 1017276479Sdim if (N->getAlignment() < 2) 1018276479Sdim report_fatal_error("atomic store must be aligned"); 1019276479Sdim return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), 1020276479Sdim N->getBasePtr(), N->getPointerInfo(), MVT::i16, 1021276479Sdim N->isVolatile(), N->isNonTemporal(), 1022280031Sdim N->getAlignment(), N->getAAInfo()); 1023276479Sdim } 1024276479Sdim if (N->getMemoryVT() == MVT::i8) 1025276479Sdim return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), 1026276479Sdim N->getBasePtr(), N->getPointerInfo(), MVT::i8, 1027276479Sdim N->isVolatile(), N->isNonTemporal(), 1028280031Sdim N->getAlignment(), N->getAAInfo()); 1029276479Sdim return SDValue(); 1030276479Sdim} 1031276479Sdim 1032193323Sed//===----------------------------------------------------------------------===// 1033193323Sed// Calling Convention Implementation 1034193323Sed//===----------------------------------------------------------------------===// 1035193323Sed 1036193323Sed#include "XCoreGenCallingConv.inc" 1037193323Sed 1038193323Sed//===----------------------------------------------------------------------===// 1039198090Srdivacky// Call Calling Convention Implementation 1040193323Sed//===----------------------------------------------------------------------===// 1041193323Sed 1042198090Srdivacky/// XCore call implementation 1043198090SrdivackySDValue 1044239462SdimXCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 1045207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 1046239462Sdim SelectionDAG &DAG = CLI.DAG; 1047261991Sdim SDLoc &dl = CLI.DL; 1048261991Sdim SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 1049261991Sdim SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 1050261991Sdim SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 1051239462Sdim SDValue Chain = CLI.Chain; 1052239462Sdim SDValue Callee = CLI.Callee; 1053239462Sdim bool &isTailCall = CLI.IsTailCall; 1054239462Sdim CallingConv::ID CallConv = CLI.CallConv; 1055239462Sdim bool isVarArg = CLI.IsVarArg; 1056239462Sdim 1057203954Srdivacky // XCore target does not yet support tail call optimization. 1058203954Srdivacky isTailCall = false; 1059198090Srdivacky 1060193323Sed // For now, only CallingConv::C implemented 1061198090Srdivacky switch (CallConv) 1062193323Sed { 1063193323Sed default: 1064198090Srdivacky llvm_unreachable("Unsupported calling convention"); 1065193323Sed case CallingConv::Fast: 1066193323Sed case CallingConv::C: 1067198090Srdivacky return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 1068210299Sed Outs, OutVals, Ins, dl, DAG, InVals); 1069193323Sed } 1070193323Sed} 1071193323Sed 1072276479Sdim/// LowerCallResult - Lower the result values of a call into the 1073276479Sdim/// appropriate copies out of appropriate physical registers / memory locations. 1074276479Sdimstatic SDValue 1075276479SdimLowerCallResult(SDValue Chain, SDValue InFlag, 1076276479Sdim const SmallVectorImpl<CCValAssign> &RVLocs, 1077276479Sdim SDLoc dl, SelectionDAG &DAG, 1078276479Sdim SmallVectorImpl<SDValue> &InVals) { 1079276479Sdim SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs; 1080276479Sdim // Copy results out of physical registers. 1081276479Sdim for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1082276479Sdim const CCValAssign &VA = RVLocs[i]; 1083276479Sdim if (VA.isRegLoc()) { 1084276479Sdim Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), 1085276479Sdim InFlag).getValue(1); 1086276479Sdim InFlag = Chain.getValue(2); 1087276479Sdim InVals.push_back(Chain.getValue(0)); 1088276479Sdim } else { 1089276479Sdim assert(VA.isMemLoc()); 1090276479Sdim ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(), 1091276479Sdim InVals.size())); 1092276479Sdim // Reserve space for this result. 1093276479Sdim InVals.push_back(SDValue()); 1094276479Sdim } 1095276479Sdim } 1096276479Sdim 1097276479Sdim // Copy results out of memory. 1098276479Sdim SmallVector<SDValue, 4> MemOpChains; 1099276479Sdim for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) { 1100276479Sdim int offset = ResultMemLocs[i].first; 1101276479Sdim unsigned index = ResultMemLocs[i].second; 1102276479Sdim SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); 1103288943Sdim SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) }; 1104276479Sdim SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops); 1105276479Sdim InVals[index] = load; 1106276479Sdim MemOpChains.push_back(load.getValue(1)); 1107276479Sdim } 1108276479Sdim 1109276479Sdim // Transform all loads nodes into one single node because 1110276479Sdim // all load nodes are independent of each other. 1111276479Sdim if (!MemOpChains.empty()) 1112276479Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 1113276479Sdim 1114276479Sdim return Chain; 1115276479Sdim} 1116276479Sdim 1117193323Sed/// LowerCCCCallTo - functions arguments are copied from virtual 1118193323Sed/// regs to (physical regs)/(stack frame), CALLSEQ_START and 1119193323Sed/// CALLSEQ_END are emitted. 1120193323Sed/// TODO: isTailCall, sret. 1121198090SrdivackySDValue 1122198090SrdivackyXCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 1123198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 1124198090Srdivacky bool isTailCall, 1125198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 1126210299Sed const SmallVectorImpl<SDValue> &OutVals, 1127198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 1128261991Sdim SDLoc dl, SelectionDAG &DAG, 1129207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 1130193323Sed 1131193323Sed // Analyze operands of the call, assigning locations to each operand. 1132193323Sed SmallVector<CCValAssign, 16> ArgLocs; 1133280031Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1134280031Sdim *DAG.getContext()); 1135193323Sed 1136193323Sed // The ABI dictates there should be one stack slot available to the callee 1137193323Sed // on function entry (for saving lr). 1138193323Sed CCInfo.AllocateStack(4, 4); 1139193323Sed 1140198090Srdivacky CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 1141193323Sed 1142276479Sdim SmallVector<CCValAssign, 16> RVLocs; 1143276479Sdim // Analyze return values to determine the number of bytes of stack required. 1144280031Sdim CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1145280031Sdim *DAG.getContext()); 1146276479Sdim RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4); 1147276479Sdim RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore); 1148276479Sdim 1149193323Sed // Get a count of how many bytes are to be pushed on the stack. 1150276479Sdim unsigned NumBytes = RetCCInfo.getNextStackOffset(); 1151288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 1152193323Sed 1153288943Sdim Chain = DAG.getCALLSEQ_START(Chain, 1154288943Sdim DAG.getConstant(NumBytes, dl, PtrVT, true), dl); 1155193323Sed 1156193323Sed SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 1157193323Sed SmallVector<SDValue, 12> MemOpChains; 1158193323Sed 1159193323Sed // Walk the register/memloc assignments, inserting copies/loads. 1160193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1161193323Sed CCValAssign &VA = ArgLocs[i]; 1162210299Sed SDValue Arg = OutVals[i]; 1163193323Sed 1164193323Sed // Promote the value if needed. 1165193323Sed switch (VA.getLocInfo()) { 1166198090Srdivacky default: llvm_unreachable("Unknown loc info!"); 1167193323Sed case CCValAssign::Full: break; 1168193323Sed case CCValAssign::SExt: 1169193323Sed Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1170193323Sed break; 1171193323Sed case CCValAssign::ZExt: 1172193323Sed Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1173193323Sed break; 1174193323Sed case CCValAssign::AExt: 1175193323Sed Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1176193323Sed break; 1177193323Sed } 1178219077Sdim 1179219077Sdim // Arguments that can be passed on register must be kept at 1180193323Sed // RegsToPass vector 1181193323Sed if (VA.isRegLoc()) { 1182193323Sed RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1183193323Sed } else { 1184193323Sed assert(VA.isMemLoc()); 1185193323Sed 1186193323Sed int Offset = VA.getLocMemOffset(); 1187193323Sed 1188219077Sdim MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, 1189193323Sed Chain, Arg, 1190288943Sdim DAG.getConstant(Offset/4, dl, 1191288943Sdim MVT::i32))); 1192193323Sed } 1193193323Sed } 1194193323Sed 1195193323Sed // Transform all store nodes into one single node because 1196193323Sed // all store nodes are independent of each other. 1197193323Sed if (!MemOpChains.empty()) 1198276479Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 1199193323Sed 1200219077Sdim // Build a sequence of copy-to-reg nodes chained together with token 1201193323Sed // chain and flag operands which copy the outgoing args into registers. 1202221345Sdim // The InFlag in necessary since all emitted instructions must be 1203193323Sed // stuck together. 1204193323Sed SDValue InFlag; 1205193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1206219077Sdim Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1207193323Sed RegsToPass[i].second, InFlag); 1208193323Sed InFlag = Chain.getValue(1); 1209193323Sed } 1210193323Sed 1211193323Sed // If the callee is a GlobalAddress node (quite common, every direct call is) 1212193323Sed // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1213193323Sed // Likewise ExternalSymbol -> TargetExternalSymbol. 1214193323Sed if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1215210299Sed Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 1216193323Sed else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1217193323Sed Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 1218193323Sed 1219193323Sed // XCoreBranchLink = #chain, #target_address, #opt_in_flags... 1220219077Sdim // = Chain, Callee, Reg#1, Reg#2, ... 1221193323Sed // 1222193323Sed // Returns a chain & a flag for retval copy to use. 1223218893Sdim SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1224193323Sed SmallVector<SDValue, 8> Ops; 1225193323Sed Ops.push_back(Chain); 1226193323Sed Ops.push_back(Callee); 1227193323Sed 1228219077Sdim // Add argument registers to the end of the list so that they are 1229193323Sed // known live into the call. 1230193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1231193323Sed Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1232193323Sed RegsToPass[i].second.getValueType())); 1233193323Sed 1234193323Sed if (InFlag.getNode()) 1235193323Sed Ops.push_back(InFlag); 1236193323Sed 1237276479Sdim Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops); 1238193323Sed InFlag = Chain.getValue(1); 1239193323Sed 1240193323Sed // Create the CALLSEQ_END node. 1241288943Sdim Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true), 1242288943Sdim DAG.getConstant(0, dl, PtrVT, true), InFlag, dl); 1243193323Sed InFlag = Chain.getValue(1); 1244193323Sed 1245193323Sed // Handle result values, copying them out of physregs into vregs that we 1246193323Sed // return. 1247276479Sdim return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); 1248193323Sed} 1249193323Sed 1250193323Sed//===----------------------------------------------------------------------===// 1251198090Srdivacky// Formal Arguments Calling Convention Implementation 1252193323Sed//===----------------------------------------------------------------------===// 1253193323Sed 1254261991Sdimnamespace { 1255261991Sdim struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; }; 1256261991Sdim} 1257261991Sdim 1258198090Srdivacky/// XCore formal arguments implementation 1259198090SrdivackySDValue 1260198090SrdivackyXCoreTargetLowering::LowerFormalArguments(SDValue Chain, 1261198090Srdivacky CallingConv::ID CallConv, 1262198090Srdivacky bool isVarArg, 1263198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 1264261991Sdim SDLoc dl, 1265198090Srdivacky SelectionDAG &DAG, 1266207618Srdivacky SmallVectorImpl<SDValue> &InVals) 1267207618Srdivacky const { 1268198090Srdivacky switch (CallConv) 1269193323Sed { 1270193323Sed default: 1271198090Srdivacky llvm_unreachable("Unsupported calling convention"); 1272193323Sed case CallingConv::C: 1273193323Sed case CallingConv::Fast: 1274198090Srdivacky return LowerCCCArguments(Chain, CallConv, isVarArg, 1275198090Srdivacky Ins, dl, DAG, InVals); 1276193323Sed } 1277193323Sed} 1278193323Sed 1279193323Sed/// LowerCCCArguments - transform physical registers into 1280193323Sed/// virtual registers and generate load operations for 1281193323Sed/// arguments places on the stack. 1282193323Sed/// TODO: sret 1283198090SrdivackySDValue 1284198090SrdivackyXCoreTargetLowering::LowerCCCArguments(SDValue Chain, 1285198090Srdivacky CallingConv::ID CallConv, 1286198090Srdivacky bool isVarArg, 1287198090Srdivacky const SmallVectorImpl<ISD::InputArg> 1288198090Srdivacky &Ins, 1289261991Sdim SDLoc dl, 1290198090Srdivacky SelectionDAG &DAG, 1291207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 1292193323Sed MachineFunction &MF = DAG.getMachineFunction(); 1293193323Sed MachineFrameInfo *MFI = MF.getFrameInfo(); 1294193323Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1295276479Sdim XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 1296193323Sed 1297193323Sed // Assign locations to all of the incoming arguments. 1298193323Sed SmallVector<CCValAssign, 16> ArgLocs; 1299280031Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1300280031Sdim *DAG.getContext()); 1301193323Sed 1302198090Srdivacky CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); 1303193323Sed 1304218893Sdim unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize(); 1305193323Sed 1306193323Sed unsigned LRSaveSize = StackSlotSize; 1307219077Sdim 1308276479Sdim if (!isVarArg) 1309276479Sdim XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize); 1310276479Sdim 1311261991Sdim // All getCopyFromReg ops must precede any getMemcpys to prevent the 1312261991Sdim // scheduler clobbering a register before it has been copied. 1313261991Sdim // The stages are: 1314261991Sdim // 1. CopyFromReg (and load) arg & vararg registers. 1315261991Sdim // 2. Chain CopyFromReg nodes into a TokenFactor. 1316261991Sdim // 3. Memcpy 'byVal' args & push final InVals. 1317261991Sdim // 4. Chain mem ops nodes into a TokenFactor. 1318261991Sdim SmallVector<SDValue, 4> CFRegNode; 1319261991Sdim SmallVector<ArgDataPair, 4> ArgData; 1320261991Sdim SmallVector<SDValue, 4> MemOps; 1321261991Sdim 1322261991Sdim // 1a. CopyFromReg (and load) arg registers. 1323193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1324193323Sed 1325193323Sed CCValAssign &VA = ArgLocs[i]; 1326261991Sdim SDValue ArgIn; 1327219077Sdim 1328193323Sed if (VA.isRegLoc()) { 1329193323Sed // Arguments passed in registers 1330198090Srdivacky EVT RegVT = VA.getLocVT(); 1331198090Srdivacky switch (RegVT.getSimpleVT().SimpleTy) { 1332193323Sed default: 1333198090Srdivacky { 1334198090Srdivacky#ifndef NDEBUG 1335198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 1336198090Srdivacky << RegVT.getSimpleVT().SimpleTy << "\n"; 1337198090Srdivacky#endif 1338276479Sdim llvm_unreachable(nullptr); 1339198090Srdivacky } 1340193323Sed case MVT::i32: 1341239462Sdim unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1342193323Sed RegInfo.addLiveIn(VA.getLocReg(), VReg); 1343261991Sdim ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 1344261991Sdim CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1)); 1345193323Sed } 1346193323Sed } else { 1347193323Sed // sanity check 1348193323Sed assert(VA.isMemLoc()); 1349193323Sed // Load the argument to a virtual register 1350193323Sed unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 1351193323Sed if (ObjSize > StackSlotSize) { 1352198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 1353218893Sdim << EVT(VA.getLocVT()).getEVTString() 1354198090Srdivacky << "\n"; 1355193323Sed } 1356193323Sed // Create the frame index object for this incoming parameter... 1357193323Sed int FI = MFI->CreateFixedObject(ObjSize, 1358199481Srdivacky LRSaveSize + VA.getLocMemOffset(), 1359210299Sed true); 1360193323Sed 1361193323Sed // Create the SelectionDAG nodes corresponding to a load 1362193323Sed //from this parameter 1363193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1364261991Sdim ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 1365296417Sdim MachinePointerInfo::getFixedStack(MF, FI), false, 1366296417Sdim false, false, 0); 1367193323Sed } 1368261991Sdim const ArgDataPair ADP = { ArgIn, Ins[i].Flags }; 1369261991Sdim ArgData.push_back(ADP); 1370193323Sed } 1371219077Sdim 1372261991Sdim // 1b. CopyFromReg vararg registers. 1373193323Sed if (isVarArg) { 1374261991Sdim // Argument registers 1375276479Sdim static const MCPhysReg ArgRegs[] = { 1376193323Sed XCore::R0, XCore::R1, XCore::R2, XCore::R3 1377193323Sed }; 1378193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 1379288943Sdim unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); 1380193323Sed if (FirstVAReg < array_lengthof(ArgRegs)) { 1381193323Sed int offset = 0; 1382193323Sed // Save remaining registers, storing higher register numbers at a higher 1383193323Sed // address 1384226633Sdim for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { 1385193323Sed // Create a stack slot 1386210299Sed int FI = MFI->CreateFixedObject(4, offset, true); 1387226633Sdim if (i == (int)FirstVAReg) { 1388193323Sed XFI->setVarArgsFrameIndex(FI); 1389193323Sed } 1390193323Sed offset -= StackSlotSize; 1391193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1392193323Sed // Move argument from phys reg -> virt reg 1393239462Sdim unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1394193323Sed RegInfo.addLiveIn(ArgRegs[i], VReg); 1395198090Srdivacky SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1396261991Sdim CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1)); 1397193323Sed // Move argument from virt reg -> stack 1398218893Sdim SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1399218893Sdim MachinePointerInfo(), false, false, 0); 1400193323Sed MemOps.push_back(Store); 1401193323Sed } 1402193323Sed } else { 1403193323Sed // This will point to the next argument passed via stack. 1404193323Sed XFI->setVarArgsFrameIndex( 1405199481Srdivacky MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(), 1406210299Sed true)); 1407193323Sed } 1408193323Sed } 1409219077Sdim 1410261991Sdim // 2. chain CopyFromReg nodes into a TokenFactor. 1411261991Sdim if (!CFRegNode.empty()) 1412276479Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode); 1413261991Sdim 1414261991Sdim // 3. Memcpy 'byVal' args & push final InVals. 1415261991Sdim // Aggregates passed "byVal" need to be copied by the callee. 1416261991Sdim // The callee will use a pointer to this copy, rather than the original 1417261991Sdim // pointer. 1418261991Sdim for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(), 1419261991Sdim ArgDE = ArgData.end(); 1420261991Sdim ArgDI != ArgDE; ++ArgDI) { 1421261991Sdim if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) { 1422261991Sdim unsigned Size = ArgDI->Flags.getByValSize(); 1423261991Sdim unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign()); 1424261991Sdim // Create a new object on the stack and copy the pointee into it. 1425276479Sdim int FI = MFI->CreateStackObject(Size, Align, false); 1426261991Sdim SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1427261991Sdim InVals.push_back(FIN); 1428261991Sdim MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, 1429288943Sdim DAG.getConstant(Size, dl, MVT::i32), 1430288943Sdim Align, false, false, false, 1431261991Sdim MachinePointerInfo(), 1432261991Sdim MachinePointerInfo())); 1433261991Sdim } else { 1434261991Sdim InVals.push_back(ArgDI->SDV); 1435261991Sdim } 1436261991Sdim } 1437261991Sdim 1438261991Sdim // 4, chain mem ops nodes into a TokenFactor. 1439261991Sdim if (!MemOps.empty()) { 1440261991Sdim MemOps.push_back(Chain); 1441276479Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); 1442261991Sdim } 1443261991Sdim 1444198090Srdivacky return Chain; 1445193323Sed} 1446193323Sed 1447193323Sed//===----------------------------------------------------------------------===// 1448193323Sed// Return Value Calling Convention Implementation 1449193323Sed//===----------------------------------------------------------------------===// 1450193323Sed 1451199481Srdivackybool XCoreTargetLowering:: 1452223017SdimCanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1453239462Sdim bool isVarArg, 1454210299Sed const SmallVectorImpl<ISD::OutputArg> &Outs, 1455210299Sed LLVMContext &Context) const { 1456199481Srdivacky SmallVector<CCValAssign, 16> RVLocs; 1457280031Sdim CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 1458276479Sdim if (!CCInfo.CheckReturn(Outs, RetCC_XCore)) 1459276479Sdim return false; 1460276479Sdim if (CCInfo.getNextStackOffset() != 0 && isVarArg) 1461276479Sdim return false; 1462276479Sdim return true; 1463199481Srdivacky} 1464199481Srdivacky 1465198090SrdivackySDValue 1466198090SrdivackyXCoreTargetLowering::LowerReturn(SDValue Chain, 1467198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 1468198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 1469210299Sed const SmallVectorImpl<SDValue> &OutVals, 1470261991Sdim SDLoc dl, SelectionDAG &DAG) const { 1471198090Srdivacky 1472276479Sdim XCoreFunctionInfo *XFI = 1473276479Sdim DAG.getMachineFunction().getInfo<XCoreFunctionInfo>(); 1474276479Sdim MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1475276479Sdim 1476193323Sed // CCValAssign - represent the assignment of 1477193323Sed // the return value to a location 1478193323Sed SmallVector<CCValAssign, 16> RVLocs; 1479193323Sed 1480193323Sed // CCState - Info about the registers and stack slot. 1481280031Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1482280031Sdim *DAG.getContext()); 1483193323Sed 1484223017Sdim // Analyze return values. 1485276479Sdim if (!isVarArg) 1486276479Sdim CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4); 1487276479Sdim 1488198090Srdivacky CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 1489193323Sed 1490193323Sed SDValue Flag; 1491249423Sdim SmallVector<SDValue, 4> RetOps(1, Chain); 1492193323Sed 1493249423Sdim // Return on XCore is always a "retsp 0" 1494288943Sdim RetOps.push_back(DAG.getConstant(0, dl, MVT::i32)); 1495249423Sdim 1496276479Sdim SmallVector<SDValue, 4> MemOpChains; 1497276479Sdim // Handle return values that must be copied to memory. 1498276479Sdim for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1499193323Sed CCValAssign &VA = RVLocs[i]; 1500276479Sdim if (VA.isRegLoc()) 1501276479Sdim continue; 1502276479Sdim assert(VA.isMemLoc()); 1503276479Sdim if (isVarArg) { 1504276479Sdim report_fatal_error("Can't return value from vararg function in memory"); 1505276479Sdim } 1506193323Sed 1507276479Sdim int Offset = VA.getLocMemOffset(); 1508276479Sdim unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; 1509276479Sdim // Create the frame index object for the memory location. 1510276479Sdim int FI = MFI->CreateFixedObject(ObjSize, Offset, false); 1511193323Sed 1512276479Sdim // Create a SelectionDAG node corresponding to a store 1513276479Sdim // to this memory location. 1514276479Sdim SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1515296417Sdim MemOpChains.push_back(DAG.getStore( 1516296417Sdim Chain, dl, OutVals[i], FIN, 1517296417Sdim MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false, 1518296417Sdim false, 0)); 1519276479Sdim } 1520276479Sdim 1521276479Sdim // Transform all store nodes into one single node because 1522276479Sdim // all stores are independent of each other. 1523276479Sdim if (!MemOpChains.empty()) 1524276479Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 1525276479Sdim 1526276479Sdim // Now handle return values copied to registers. 1527276479Sdim for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1528276479Sdim CCValAssign &VA = RVLocs[i]; 1529276479Sdim if (!VA.isRegLoc()) 1530276479Sdim continue; 1531276479Sdim // Copy the result values into the output registers. 1532276479Sdim Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 1533276479Sdim 1534193323Sed // guarantee that all emitted copies are 1535193323Sed // stuck together, avoiding something bad 1536193323Sed Flag = Chain.getValue(1); 1537249423Sdim RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1538193323Sed } 1539193323Sed 1540249423Sdim RetOps[0] = Chain; // Update chain. 1541249423Sdim 1542249423Sdim // Add the flag if we have it. 1543193323Sed if (Flag.getNode()) 1544249423Sdim RetOps.push_back(Flag); 1545249423Sdim 1546276479Sdim return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps); 1547193323Sed} 1548193323Sed 1549193323Sed//===----------------------------------------------------------------------===// 1550193323Sed// Other Lowering Code 1551193323Sed//===----------------------------------------------------------------------===// 1552193323Sed 1553193323SedMachineBasicBlock * 1554193323SedXCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1555207618Srdivacky MachineBasicBlock *BB) const { 1556288943Sdim const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1557193323Sed DebugLoc dl = MI->getDebugLoc(); 1558193323Sed assert((MI->getOpcode() == XCore::SELECT_CC) && 1559193323Sed "Unexpected instr type to insert"); 1560219077Sdim 1561193323Sed // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1562193323Sed // control-flow pattern. The incoming instruction knows the destination vreg 1563193323Sed // to set, the condition code register to branch on, the true/false values to 1564193323Sed // select between, and a branch opcode to use. 1565193323Sed const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1566296417Sdim MachineFunction::iterator It = ++BB->getIterator(); 1567219077Sdim 1568193323Sed // thisMBB: 1569193323Sed // ... 1570193323Sed // TrueVal = ... 1571193323Sed // cmpTY ccX, r1, r2 1572193323Sed // bCC copy1MBB 1573193323Sed // fallthrough --> copy0MBB 1574193323Sed MachineBasicBlock *thisMBB = BB; 1575193323Sed MachineFunction *F = BB->getParent(); 1576193323Sed MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1577193323Sed MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1578193323Sed F->insert(It, copy0MBB); 1579193323Sed F->insert(It, sinkMBB); 1580210299Sed 1581210299Sed // Transfer the remainder of BB and its successor edges to sinkMBB. 1582210299Sed sinkMBB->splice(sinkMBB->begin(), BB, 1583276479Sdim std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1584210299Sed sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1585210299Sed 1586193323Sed // Next, add the true and fallthrough blocks as its successors. 1587193323Sed BB->addSuccessor(copy0MBB); 1588193323Sed BB->addSuccessor(sinkMBB); 1589219077Sdim 1590210299Sed BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1591210299Sed .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1592210299Sed 1593193323Sed // copy0MBB: 1594193323Sed // %FalseValue = ... 1595193323Sed // # fallthrough to sinkMBB 1596193323Sed BB = copy0MBB; 1597219077Sdim 1598193323Sed // Update machine-CFG edges 1599193323Sed BB->addSuccessor(sinkMBB); 1600219077Sdim 1601193323Sed // sinkMBB: 1602193323Sed // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1603193323Sed // ... 1604193323Sed BB = sinkMBB; 1605210299Sed BuildMI(*BB, BB->begin(), dl, 1606210299Sed TII.get(XCore::PHI), MI->getOperand(0).getReg()) 1607193323Sed .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1608193323Sed .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1609219077Sdim 1610210299Sed MI->eraseFromParent(); // The pseudo instruction is gone now. 1611193323Sed return BB; 1612193323Sed} 1613193323Sed 1614193323Sed//===----------------------------------------------------------------------===// 1615198090Srdivacky// Target Optimization Hooks 1616198090Srdivacky//===----------------------------------------------------------------------===// 1617198090Srdivacky 1618198090SrdivackySDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, 1619198090Srdivacky DAGCombinerInfo &DCI) const { 1620198090Srdivacky SelectionDAG &DAG = DCI.DAG; 1621261991Sdim SDLoc dl(N); 1622198090Srdivacky switch (N->getOpcode()) { 1623198090Srdivacky default: break; 1624276479Sdim case ISD::INTRINSIC_VOID: 1625276479Sdim switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 1626276479Sdim case Intrinsic::xcore_outt: 1627276479Sdim case Intrinsic::xcore_outct: 1628276479Sdim case Intrinsic::xcore_chkct: { 1629276479Sdim SDValue OutVal = N->getOperand(3); 1630276479Sdim // These instructions ignore the high bits. 1631276479Sdim if (OutVal.hasOneUse()) { 1632276479Sdim unsigned BitWidth = OutVal.getValueSizeInBits(); 1633276479Sdim APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8); 1634276479Sdim APInt KnownZero, KnownOne; 1635276479Sdim TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 1636276479Sdim !DCI.isBeforeLegalizeOps()); 1637276479Sdim const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1638276479Sdim if (TLO.ShrinkDemandedConstant(OutVal, DemandedMask) || 1639276479Sdim TLI.SimplifyDemandedBits(OutVal, DemandedMask, KnownZero, KnownOne, 1640276479Sdim TLO)) 1641276479Sdim DCI.CommitTargetLoweringOpt(TLO); 1642276479Sdim } 1643276479Sdim break; 1644276479Sdim } 1645276479Sdim case Intrinsic::xcore_setpt: { 1646276479Sdim SDValue Time = N->getOperand(3); 1647276479Sdim // This instruction ignores the high bits. 1648276479Sdim if (Time.hasOneUse()) { 1649276479Sdim unsigned BitWidth = Time.getValueSizeInBits(); 1650276479Sdim APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16); 1651276479Sdim APInt KnownZero, KnownOne; 1652276479Sdim TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 1653276479Sdim !DCI.isBeforeLegalizeOps()); 1654276479Sdim const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1655276479Sdim if (TLO.ShrinkDemandedConstant(Time, DemandedMask) || 1656276479Sdim TLI.SimplifyDemandedBits(Time, DemandedMask, KnownZero, KnownOne, 1657276479Sdim TLO)) 1658276479Sdim DCI.CommitTargetLoweringOpt(TLO); 1659276479Sdim } 1660276479Sdim break; 1661276479Sdim } 1662276479Sdim } 1663276479Sdim break; 1664204961Srdivacky case XCoreISD::LADD: { 1665204961Srdivacky SDValue N0 = N->getOperand(0); 1666204961Srdivacky SDValue N1 = N->getOperand(1); 1667204961Srdivacky SDValue N2 = N->getOperand(2); 1668204961Srdivacky ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1669204961Srdivacky ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1670204961Srdivacky EVT VT = N0.getValueType(); 1671204961Srdivacky 1672204961Srdivacky // canonicalize constant to RHS 1673204961Srdivacky if (N0C && !N1C) 1674204961Srdivacky return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); 1675204961Srdivacky 1676204961Srdivacky // fold (ladd 0, 0, x) -> 0, x & 1 1677204961Srdivacky if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1678288943Sdim SDValue Carry = DAG.getConstant(0, dl, VT); 1679204961Srdivacky SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, 1680288943Sdim DAG.getConstant(1, dl, VT)); 1681249423Sdim SDValue Ops[] = { Result, Carry }; 1682276479Sdim return DAG.getMergeValues(Ops, dl); 1683204961Srdivacky } 1684204961Srdivacky 1685204961Srdivacky // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the 1686204961Srdivacky // low bit set 1687249423Sdim if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1688204961Srdivacky APInt KnownZero, KnownOne; 1689204961Srdivacky APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1690204961Srdivacky VT.getSizeInBits() - 1); 1691276479Sdim DAG.computeKnownBits(N2, KnownZero, KnownOne); 1692234353Sdim if ((KnownZero & Mask) == Mask) { 1693288943Sdim SDValue Carry = DAG.getConstant(0, dl, VT); 1694204961Srdivacky SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); 1695249423Sdim SDValue Ops[] = { Result, Carry }; 1696276479Sdim return DAG.getMergeValues(Ops, dl); 1697204961Srdivacky } 1698204961Srdivacky } 1699204961Srdivacky } 1700204961Srdivacky break; 1701204961Srdivacky case XCoreISD::LSUB: { 1702204961Srdivacky SDValue N0 = N->getOperand(0); 1703204961Srdivacky SDValue N1 = N->getOperand(1); 1704204961Srdivacky SDValue N2 = N->getOperand(2); 1705204961Srdivacky ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1706204961Srdivacky ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1707204961Srdivacky EVT VT = N0.getValueType(); 1708204961Srdivacky 1709204961Srdivacky // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set 1710219077Sdim if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1711204961Srdivacky APInt KnownZero, KnownOne; 1712204961Srdivacky APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1713204961Srdivacky VT.getSizeInBits() - 1); 1714276479Sdim DAG.computeKnownBits(N2, KnownZero, KnownOne); 1715234353Sdim if ((KnownZero & Mask) == Mask) { 1716204961Srdivacky SDValue Borrow = N2; 1717204961Srdivacky SDValue Result = DAG.getNode(ISD::SUB, dl, VT, 1718288943Sdim DAG.getConstant(0, dl, VT), N2); 1719249423Sdim SDValue Ops[] = { Result, Borrow }; 1720276479Sdim return DAG.getMergeValues(Ops, dl); 1721204961Srdivacky } 1722204961Srdivacky } 1723204961Srdivacky 1724204961Srdivacky // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the 1725204961Srdivacky // low bit set 1726249423Sdim if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1727204961Srdivacky APInt KnownZero, KnownOne; 1728204961Srdivacky APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1729204961Srdivacky VT.getSizeInBits() - 1); 1730276479Sdim DAG.computeKnownBits(N2, KnownZero, KnownOne); 1731234353Sdim if ((KnownZero & Mask) == Mask) { 1732288943Sdim SDValue Borrow = DAG.getConstant(0, dl, VT); 1733204961Srdivacky SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); 1734249423Sdim SDValue Ops[] = { Result, Borrow }; 1735276479Sdim return DAG.getMergeValues(Ops, dl); 1736204961Srdivacky } 1737204961Srdivacky } 1738204961Srdivacky } 1739204961Srdivacky break; 1740205218Srdivacky case XCoreISD::LMUL: { 1741205218Srdivacky SDValue N0 = N->getOperand(0); 1742205218Srdivacky SDValue N1 = N->getOperand(1); 1743205218Srdivacky SDValue N2 = N->getOperand(2); 1744205218Srdivacky SDValue N3 = N->getOperand(3); 1745205218Srdivacky ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1746205218Srdivacky ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1747205218Srdivacky EVT VT = N0.getValueType(); 1748205218Srdivacky // Canonicalize multiplicative constant to RHS. If both multiplicative 1749205218Srdivacky // operands are constant canonicalize smallest to RHS. 1750205218Srdivacky if ((N0C && !N1C) || 1751205218Srdivacky (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue())) 1752226633Sdim return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), 1753226633Sdim N1, N0, N2, N3); 1754205218Srdivacky 1755205218Srdivacky // lmul(x, 0, a, b) 1756205218Srdivacky if (N1C && N1C->isNullValue()) { 1757205218Srdivacky // If the high result is unused fold to add(a, b) 1758205218Srdivacky if (N->hasNUsesOfValue(0, 0)) { 1759205218Srdivacky SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); 1760249423Sdim SDValue Ops[] = { Lo, Lo }; 1761276479Sdim return DAG.getMergeValues(Ops, dl); 1762205218Srdivacky } 1763205218Srdivacky // Otherwise fold to ladd(a, b, 0) 1764249423Sdim SDValue Result = 1765249423Sdim DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); 1766249423Sdim SDValue Carry(Result.getNode(), 1); 1767249423Sdim SDValue Ops[] = { Carry, Result }; 1768276479Sdim return DAG.getMergeValues(Ops, dl); 1769205218Srdivacky } 1770205218Srdivacky } 1771205218Srdivacky break; 1772204961Srdivacky case ISD::ADD: { 1773205218Srdivacky // Fold 32 bit expressions such as add(add(mul(x,y),a),b) -> 1774205218Srdivacky // lmul(x, y, a, b). The high result of lmul will be ignored. 1775204961Srdivacky // This is only profitable if the intermediate results are unused 1776204961Srdivacky // elsewhere. 1777204961Srdivacky SDValue Mul0, Mul1, Addend0, Addend1; 1778205218Srdivacky if (N->getValueType(0) == MVT::i32 && 1779205218Srdivacky isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { 1780204961Srdivacky SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, 1781204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), Mul0, 1782204961Srdivacky Mul1, Addend0, Addend1); 1783204961Srdivacky SDValue Result(Ignored.getNode(), 1); 1784204961Srdivacky return Result; 1785204961Srdivacky } 1786205218Srdivacky APInt HighMask = APInt::getHighBitsSet(64, 32); 1787205218Srdivacky // Fold 64 bit expression such as add(add(mul(x,y),a),b) -> 1788205218Srdivacky // lmul(x, y, a, b) if all operands are zero-extended. We do this 1789205218Srdivacky // before type legalization as it is messy to match the operands after 1790205218Srdivacky // that. 1791205218Srdivacky if (N->getValueType(0) == MVT::i64 && 1792205218Srdivacky isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && 1793205218Srdivacky DAG.MaskedValueIsZero(Mul0, HighMask) && 1794205218Srdivacky DAG.MaskedValueIsZero(Mul1, HighMask) && 1795205218Srdivacky DAG.MaskedValueIsZero(Addend0, HighMask) && 1796205218Srdivacky DAG.MaskedValueIsZero(Addend1, HighMask)) { 1797205218Srdivacky SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1798288943Sdim Mul0, DAG.getConstant(0, dl, MVT::i32)); 1799205218Srdivacky SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1800288943Sdim Mul1, DAG.getConstant(0, dl, MVT::i32)); 1801205218Srdivacky SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1802288943Sdim Addend0, DAG.getConstant(0, dl, MVT::i32)); 1803205218Srdivacky SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1804288943Sdim Addend1, DAG.getConstant(0, dl, MVT::i32)); 1805205218Srdivacky SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 1806205218Srdivacky DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, 1807205218Srdivacky Addend0L, Addend1L); 1808205218Srdivacky SDValue Lo(Hi.getNode(), 1); 1809205218Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 1810205218Srdivacky } 1811204961Srdivacky } 1812204961Srdivacky break; 1813198090Srdivacky case ISD::STORE: { 1814198090Srdivacky // Replace unaligned store of unaligned load with memmove. 1815198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(N); 1816198090Srdivacky if (!DCI.isBeforeLegalize() || 1817280031Sdim allowsMisalignedMemoryAccesses(ST->getMemoryVT(), 1818280031Sdim ST->getAddressSpace(), 1819280031Sdim ST->getAlignment()) || 1820198090Srdivacky ST->isVolatile() || ST->isIndexed()) { 1821198090Srdivacky break; 1822198090Srdivacky } 1823198090Srdivacky SDValue Chain = ST->getChain(); 1824198090Srdivacky 1825198090Srdivacky unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); 1826296417Sdim assert((StoreBits % 8) == 0 && 1827296417Sdim "Store size in bits must be a multiple of 8"); 1828288943Sdim unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment( 1829198090Srdivacky ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); 1830198090Srdivacky unsigned Alignment = ST->getAlignment(); 1831198090Srdivacky if (Alignment >= ABIAlignment) { 1832198090Srdivacky break; 1833198090Srdivacky } 1834198090Srdivacky 1835198090Srdivacky if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) { 1836198090Srdivacky if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() && 1837198090Srdivacky LD->getAlignment() == Alignment && 1838198090Srdivacky !LD->isVolatile() && !LD->isIndexed() && 1839198090Srdivacky Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { 1840288943Sdim bool isTail = isInTailCallPosition(DAG, ST, Chain); 1841198090Srdivacky return DAG.getMemmove(Chain, dl, ST->getBasePtr(), 1842198090Srdivacky LD->getBasePtr(), 1843288943Sdim DAG.getConstant(StoreBits/8, dl, MVT::i32), 1844288943Sdim Alignment, false, isTail, ST->getPointerInfo(), 1845218893Sdim LD->getPointerInfo()); 1846198090Srdivacky } 1847198090Srdivacky } 1848198090Srdivacky break; 1849198090Srdivacky } 1850198090Srdivacky } 1851198090Srdivacky return SDValue(); 1852198090Srdivacky} 1853198090Srdivacky 1854276479Sdimvoid XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, 1855276479Sdim APInt &KnownZero, 1856276479Sdim APInt &KnownOne, 1857276479Sdim const SelectionDAG &DAG, 1858276479Sdim unsigned Depth) const { 1859234353Sdim KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1860204961Srdivacky switch (Op.getOpcode()) { 1861204961Srdivacky default: break; 1862204961Srdivacky case XCoreISD::LADD: 1863204961Srdivacky case XCoreISD::LSUB: 1864249423Sdim if (Op.getResNo() == 1) { 1865204961Srdivacky // Top bits of carry / borrow are clear. 1866234353Sdim KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1867234353Sdim KnownZero.getBitWidth() - 1); 1868204961Srdivacky } 1869204961Srdivacky break; 1870276479Sdim case ISD::INTRINSIC_W_CHAIN: 1871276479Sdim { 1872276479Sdim unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 1873276479Sdim switch (IntNo) { 1874276479Sdim case Intrinsic::xcore_getts: 1875276479Sdim // High bits are known to be zero. 1876276479Sdim KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1877276479Sdim KnownZero.getBitWidth() - 16); 1878276479Sdim break; 1879276479Sdim case Intrinsic::xcore_int: 1880276479Sdim case Intrinsic::xcore_inct: 1881276479Sdim // High bits are known to be zero. 1882276479Sdim KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1883276479Sdim KnownZero.getBitWidth() - 8); 1884276479Sdim break; 1885276479Sdim case Intrinsic::xcore_testct: 1886276479Sdim // Result is either 0 or 1. 1887276479Sdim KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1888276479Sdim KnownZero.getBitWidth() - 1); 1889276479Sdim break; 1890276479Sdim case Intrinsic::xcore_testwct: 1891276479Sdim // Result is in the range 0 - 4. 1892276479Sdim KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1893276479Sdim KnownZero.getBitWidth() - 3); 1894276479Sdim break; 1895276479Sdim } 1896276479Sdim } 1897276479Sdim break; 1898204961Srdivacky } 1899204961Srdivacky} 1900204961Srdivacky 1901198090Srdivacky//===----------------------------------------------------------------------===// 1902193323Sed// Addressing mode description hooks 1903193323Sed//===----------------------------------------------------------------------===// 1904193323Sed 1905193323Sedstatic inline bool isImmUs(int64_t val) 1906193323Sed{ 1907193323Sed return (val >= 0 && val <= 11); 1908193323Sed} 1909193323Sed 1910193323Sedstatic inline bool isImmUs2(int64_t val) 1911193323Sed{ 1912193323Sed return (val%2 == 0 && isImmUs(val/2)); 1913193323Sed} 1914193323Sed 1915193323Sedstatic inline bool isImmUs4(int64_t val) 1916193323Sed{ 1917193323Sed return (val%4 == 0 && isImmUs(val/4)); 1918193323Sed} 1919193323Sed 1920193323Sed/// isLegalAddressingMode - Return true if the addressing mode represented 1921193323Sed/// by AM is legal for this target, for a load/store of the specified type. 1922288943Sdimbool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL, 1923288943Sdim const AddrMode &AM, Type *Ty, 1924288943Sdim unsigned AS) const { 1925198090Srdivacky if (Ty->getTypeID() == Type::VoidTyID) 1926204642Srdivacky return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1927198090Srdivacky 1928288943Sdim unsigned Size = DL.getTypeAllocSize(Ty); 1929193323Sed if (AM.BaseGV) { 1930198090Srdivacky return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1931193323Sed AM.BaseOffs%4 == 0; 1932193323Sed } 1933219077Sdim 1934198090Srdivacky switch (Size) { 1935198090Srdivacky case 1: 1936193323Sed // reg + imm 1937193323Sed if (AM.Scale == 0) { 1938193323Sed return isImmUs(AM.BaseOffs); 1939193323Sed } 1940198090Srdivacky // reg + reg 1941193323Sed return AM.Scale == 1 && AM.BaseOffs == 0; 1942198090Srdivacky case 2: 1943198090Srdivacky case 3: 1944193323Sed // reg + imm 1945193323Sed if (AM.Scale == 0) { 1946193323Sed return isImmUs2(AM.BaseOffs); 1947193323Sed } 1948198090Srdivacky // reg + reg<<1 1949193323Sed return AM.Scale == 2 && AM.BaseOffs == 0; 1950198090Srdivacky default: 1951193323Sed // reg + imm 1952193323Sed if (AM.Scale == 0) { 1953193323Sed return isImmUs4(AM.BaseOffs); 1954193323Sed } 1955193323Sed // reg + reg<<2 1956193323Sed return AM.Scale == 4 && AM.BaseOffs == 0; 1957193323Sed } 1958193323Sed} 1959193323Sed 1960193323Sed//===----------------------------------------------------------------------===// 1961193323Sed// XCore Inline Assembly Support 1962193323Sed//===----------------------------------------------------------------------===// 1963193323Sed 1964288943Sdimstd::pair<unsigned, const TargetRegisterClass *> 1965288943SdimXCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 1966288943Sdim StringRef Constraint, 1967288943Sdim MVT VT) const { 1968224145Sdim if (Constraint.size() == 1) { 1969224145Sdim switch (Constraint[0]) { 1970193323Sed default : break; 1971193323Sed case 'r': 1972239462Sdim return std::make_pair(0U, &XCore::GRRegsRegClass); 1973224145Sdim } 1974193323Sed } 1975224145Sdim // Use the default implementation in TargetLowering to convert the register 1976224145Sdim // constraint into a member of a register class. 1977288943Sdim return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 1978193323Sed} 1979