1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
16
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "PPCGenInstrInfo.inc"
23
24namespace llvm {
25
26/// PPCII - This namespace holds all of the PowerPC target-specific
27/// per-instruction flags.  These must match the corresponding definitions in
28/// PPC.td and PPCInstrFormats.td.
29namespace PPCII {
30enum {
31  // PPC970 Instruction Flags.  These flags describe the characteristics of the
32  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33  // raw machine instructions.
34
35  /// PPC970_First - This instruction starts a new dispatch group, so it will
36  /// always be the first one in the group.
37  PPC970_First = 0x1,
38
39  /// PPC970_Single - This instruction starts a new dispatch group and
40  /// terminates it, so it will be the sole instruction in the group.
41  PPC970_Single = 0x2,
42
43  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44  /// two dispatch pipes to be available to issue.
45  PPC970_Cracked = 0x4,
46
47  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48  /// an instruction is issued to.
49  PPC970_Shift = 3,
50  PPC970_Mask = 0x07 << PPC970_Shift
51};
52enum PPC970_Unit {
53  /// These are the various PPC970 execution unit pipelines.  Each instruction
54  /// is one of these.
55  PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
56  PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
57  PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
58  PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
59  PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
60  PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
61  PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
62  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
63};
64} // end namespace PPCII
65
66class PPCSubtarget;
67class PPCInstrInfo : public PPCGenInstrInfo {
68  PPCSubtarget &Subtarget;
69  const PPCRegisterInfo RI;
70
71  bool StoreRegToStackSlot(MachineFunction &MF,
72                           unsigned SrcReg, bool isKill, int FrameIdx,
73                           const TargetRegisterClass *RC,
74                           SmallVectorImpl<MachineInstr*> &NewMIs,
75                           bool &NonRI, bool &SpillsVRS) const;
76  bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
77                            unsigned DestReg, int FrameIdx,
78                            const TargetRegisterClass *RC,
79                            SmallVectorImpl<MachineInstr*> &NewMIs,
80                            bool &NonRI, bool &SpillsVRS) const;
81  virtual void anchor();
82
83protected:
84  /// Commutes the operands in the given instruction.
85  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
86  ///
87  /// Do not call this method for a non-commutable instruction or for
88  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
89  /// Even though the instruction is commutable, the method may still
90  /// fail to commute the operands, null pointer is returned in such cases.
91  ///
92  /// For example, we can commute rlwimi instructions, but only if the
93  /// rotate amt is zero.  We also have to munge the immediates a bit.
94  MachineInstr *commuteInstructionImpl(MachineInstr *MI,
95                                       bool NewMI,
96                                       unsigned OpIdx1,
97                                       unsigned OpIdx2) const override;
98
99public:
100  explicit PPCInstrInfo(PPCSubtarget &STI);
101
102  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
103  /// such, whenever a client has an instance of instruction info, it should
104  /// always be able to get register info as well (through this method).
105  ///
106  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
107
108  ScheduleHazardRecognizer *
109  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
110                               const ScheduleDAG *DAG) const override;
111  ScheduleHazardRecognizer *
112  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
113                                     const ScheduleDAG *DAG) const override;
114
115  unsigned getInstrLatency(const InstrItineraryData *ItinData,
116                           const MachineInstr *MI,
117                           unsigned *PredCost = nullptr) const override;
118
119  int getOperandLatency(const InstrItineraryData *ItinData,
120                        const MachineInstr *DefMI, unsigned DefIdx,
121                        const MachineInstr *UseMI,
122                        unsigned UseIdx) const override;
123  int getOperandLatency(const InstrItineraryData *ItinData,
124                        SDNode *DefNode, unsigned DefIdx,
125                        SDNode *UseNode, unsigned UseIdx) const override {
126    return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
127                                              UseNode, UseIdx);
128  }
129
130  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
131                        const MachineInstr *DefMI,
132                        unsigned DefIdx) const override {
133    // Machine LICM should hoist all instructions in low-register-pressure
134    // situations; none are sufficiently free to justify leaving in a loop
135    // body.
136    return false;
137  }
138
139  bool useMachineCombiner() const override {
140    return true;
141  }
142
143  /// Return true when there is potentially a faster code sequence
144  /// for an instruction chain ending in <Root>. All potential patterns are
145  /// output in the <Pattern> array.
146  bool getMachineCombinerPatterns(
147      MachineInstr &Root,
148      SmallVectorImpl<MachineCombinerPattern> &P) const override;
149
150  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
151
152  bool isCoalescableExtInstr(const MachineInstr &MI,
153                             unsigned &SrcReg, unsigned &DstReg,
154                             unsigned &SubIdx) const override;
155  unsigned isLoadFromStackSlot(const MachineInstr *MI,
156                               int &FrameIndex) const override;
157  unsigned isStoreToStackSlot(const MachineInstr *MI,
158                              int &FrameIndex) const override;
159
160  bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
161                             unsigned &SrcOpIdx2) const override;
162
163  void insertNoop(MachineBasicBlock &MBB,
164                  MachineBasicBlock::iterator MI) const override;
165
166
167  // Branch analysis.
168  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
169                     MachineBasicBlock *&FBB,
170                     SmallVectorImpl<MachineOperand> &Cond,
171                     bool AllowModify) const override;
172  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
173  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
174                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
175                        DebugLoc DL) const override;
176
177  // Select analysis.
178  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
179                       unsigned, unsigned, int &, int &, int &) const override;
180  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
181                    DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
182                    unsigned TrueReg, unsigned FalseReg) const override;
183
184  void copyPhysReg(MachineBasicBlock &MBB,
185                   MachineBasicBlock::iterator I, DebugLoc DL,
186                   unsigned DestReg, unsigned SrcReg,
187                   bool KillSrc) const override;
188
189  void storeRegToStackSlot(MachineBasicBlock &MBB,
190                           MachineBasicBlock::iterator MBBI,
191                           unsigned SrcReg, bool isKill, int FrameIndex,
192                           const TargetRegisterClass *RC,
193                           const TargetRegisterInfo *TRI) const override;
194
195  void loadRegFromStackSlot(MachineBasicBlock &MBB,
196                            MachineBasicBlock::iterator MBBI,
197                            unsigned DestReg, int FrameIndex,
198                            const TargetRegisterClass *RC,
199                            const TargetRegisterInfo *TRI) const override;
200
201  bool
202  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
203
204  bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
205                     unsigned Reg, MachineRegisterInfo *MRI) const override;
206
207  // If conversion by predication (only supported by some branch instructions).
208  // All of the profitability checks always return true; it is always
209  // profitable to use the predicated branches.
210  bool isProfitableToIfCvt(MachineBasicBlock &MBB,
211                          unsigned NumCycles, unsigned ExtraPredCycles,
212                          BranchProbability Probability) const override {
213    return true;
214  }
215
216  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
217                           unsigned NumT, unsigned ExtraT,
218                           MachineBasicBlock &FMBB,
219                           unsigned NumF, unsigned ExtraF,
220                           BranchProbability Probability) const override;
221
222  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
223                                 BranchProbability Probability) const override {
224    return true;
225  }
226
227  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
228                                 MachineBasicBlock &FMBB) const override {
229    return false;
230  }
231
232  // Predication support.
233  bool isPredicated(const MachineInstr *MI) const override;
234
235  bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
236
237  bool PredicateInstruction(MachineInstr *MI,
238                            ArrayRef<MachineOperand> Pred) const override;
239
240  bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
241                         ArrayRef<MachineOperand> Pred2) const override;
242
243  bool DefinesPredicate(MachineInstr *MI,
244                        std::vector<MachineOperand> &Pred) const override;
245
246  bool isPredicable(MachineInstr *MI) const override;
247
248  // Comparison optimization.
249
250
251  bool analyzeCompare(const MachineInstr *MI,
252                      unsigned &SrcReg, unsigned &SrcReg2,
253                      int &Mask, int &Value) const override;
254
255  bool optimizeCompareInstr(MachineInstr *CmpInstr,
256                            unsigned SrcReg, unsigned SrcReg2,
257                            int Mask, int Value,
258                            const MachineRegisterInfo *MRI) const override;
259
260  /// GetInstSize - Return the number of bytes of code the specified
261  /// instruction may be.  This returns the maximum number of bytes.
262  ///
263  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
264
265  void getNoopForMachoTarget(MCInst &NopInst) const override;
266
267  std::pair<unsigned, unsigned>
268  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
269
270  ArrayRef<std::pair<unsigned, const char *>>
271  getSerializableDirectMachineOperandTargetFlags() const override;
272
273  ArrayRef<std::pair<unsigned, const char *>>
274  getSerializableBitmaskMachineOperandTargetFlags() const override;
275};
276
277}
278
279#endif
280