/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 89 case MVT::i16: 482 case MVT::i16:
|
H A D | HexagonISelLoweringHVX.cpp | 1066 // A vector of i16 will be broken up into a build_vector of i16's. 1068 // all operations are expected to be type-legalized, and i16 is not 1288 // V6_vmpybv Vs, Vt produces a pair of i16 vectors Hi:Lo, 1304 case MVT::i16: 1305 // For i16 there is V6_vmpyih, which acts exactly like the MUL opcode. 1340 if (ElemTy == MVT::i8 || ElemTy == MVT::i16) { 1342 // V6_vmpybv Vs, Vt produces a pair of i16 vectors Hi:Lo, 1344 // For i16, use V6_vmpyhv, which behaves in an analogous way to
|
H A D | HexagonInstrInfo.cpp | 2648 case MVT::i16:
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 389 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 2307 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
|
H A D | LegalizeDAG.cpp | 575 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 593 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 642 // TRUNCSTORE:i16 i32 -> STORE i16 788 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 817 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2131 case MVT::i16: LC = Call_I16; break; 2188 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 2446 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2670 case MVT::i16 [all...] |
H A D | DAGCombiner.cpp | 1184 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to 1185 /// i32 since i16 instructions are longer. 1194 // If operation type is 'undesirable', e.g. i16 on x86, consider 1249 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to 1250 /// i32 since i16 instructions are longer. 1259 // If operation type is 'undesirable', e.g. i16 on x86, consider 1308 // If operation type is 'undesirable', e.g. i16 on x86, consider 1339 // If operation type is 'undesirable', e.g. i16 on x86, consider 3616 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 5348 // fold (and (extload x, i16), 25 [all...] |
H A D | SelectionDAGBuilder.cpp | 6285 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16, 7378 LoadVT = MVT::i16; 7969 // remember that AX is actually i16 to get the right extension.
|
H A D | SelectionDAG.cpp | 3990 case ISD::SEXTLOAD: // e.g. i16->i32 = '17' bits known. 3993 case ISD::ZEXTLOAD: // e.g. i16->i32 = '16' bits known. 4407 if (VT == MVT::f16 && C->getValueType(0) == MVT::i16) 4498 if (VT == MVT::i16 && C->getValueType(0) == MVT::f16)
|
H A D | TargetLowering.cpp | 2962 // Great, e.g. got icmp ult i16 (add i16 %x, 128), 256 2971 // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256 7527 if (WideVT == MVT::i16)
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 544 // Store FP status word into i16 register. 649 // Store FP control world into i16 memory. 823 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 824 /// instruction encodings are longer and some i16 instructions are slow. 829 /// i16 is legal, but undesirable since i16 instruction encodings are longer 830 /// and some i16 instructions are slow. 912 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || 1060 /// register EAX to i16 b [all...] |
H A D | X86InstrInfo.cpp | 5981 case MVT::i16:
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 475 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 2872 // Promote i8 and i16 2874 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2885 // Promote i8 and i16 2886 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 4088 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 4125 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
|
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/ |
H A D | StmtPrinter.cpp | 1140 case BuiltinType::Short: OS << "i16"; break;
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 114 for (auto VT : {MVT::i1, MVT::i8, MVT::i16}) 333 if ((MemVT == MVT::i8 || MemVT == MVT::i16 ||
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 289 // We have native instructions for i8, i16 and i32 extensions, but not i1. 4558 // Among other things, this copes with vectors like <2 x i16> that were 5739 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) 5792 if (BSwapOp.getValueType() == MVT::i16) 6075 if (LoadVT == MVT::i16) 6082 // If this is an i16 load, insert the truncate. 6084 if (N->getValueType(0) == MVT::i16) 6085 ResVal = DAG.getNode(ISD::TRUNCATE, SDLoc(N), MVT::i16, BSLoad);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 243 /// 2 for long non-rounding variants, vml{a,s}ldav[a][x]: [i16, i32] 1545 } else if (LoadedVT == MVT::i16 && 1644 case MVT::i16: 3001 else if (MemTy == MVT::i16)
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 454 case MVT::i16: \ 976 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1346 // a group of value types. For example, on i386, i8, i16, and i32 1432 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 218 for (auto T : {MVT::i8, MVT::i16, MVT::i32})
|
/freebsd-11-stable/contrib/sqlite3/ |
H A D | sqlite3.c | 14437 typedef INT16_TYPE i16; /* 2-byte signed integer */ typedef 16204 i16 nRef; /* Number of users of this page */ 17665 i16 iPKey; /* If not negative, use aCol[iPKey] as the rowid */ 17666 i16 nCol; /* Number of columns in this table */ 17667 i16 nNVCol; /* Number of columns that are not VIRTUAL */ 17953 i16 *aiColumn; /* Which columns are used by this index. 1st is 0 */ 18071 i16 iColumn; /* Column number within the source table */ 18072 i16 iSorterColumn; /* Column number in the sorting index */ 18099 typedef i16 ynVar; 18213 i16 iAg 169811 typedef short int i16; /* 2-byte (or larger) signed integer */ typedef 211802 typedef short i16; typedef [all...] |
/freebsd-11-stable/crypto/heimdal/lib/sqlite/ |
H A D | sqlite3.c | 7708 typedef INT16_TYPE i16; /* 2-byte signed integer */ typedef 8819 i16 nRef; /* Number of users of this page */ 9626 i16 nArg; /* Number of arguments. -1 means unlimited */ 10222 typedef i16 ynVar; 10322 i16 iAgg; /* Which entry in pAggInfo->aCol[] or ->aFunc[] */ 10323 i16 iRightJoinTable; /* If EP_FromJoin, the right table of the join */ 10487 i16 nSrc; /* Number of tables or subqueries in the FROM clause */ 10488 i16 nAlloc; /* Number of entries allocated in a[] below */ 114129 typedef short int i16; /* 2-byte (or larger) signed integer */ typedef [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1490 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|