Searched refs:getRegClass (Results 76 - 100 of 185) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp159 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) {
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h219 return shouldTrackSubRegLiveness(*getRegClass(VReg));
580 /// constrainRegClass(ToReg, getRegClass(FromReg))
583 /// *MRI.getRegClass(FromReg), MRI)
631 const TargetRegisterClass *getRegClass(Register Reg) const { function in class:llvm::MachineRegisterInfo
647 /// the select pass, using getRegClass is safe.
1180 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocPBQP.cpp604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
756 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
882 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
H A DMachineSink.cpp231 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
232 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
681 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
H A DTwoAddressInstructionPass.cpp1363 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1486 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1557 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1560 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1566 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
H A DRegisterCoalescer.cpp458 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
460 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
465 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
466 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
869 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
1284 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
1325 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1797 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1798 auto DstRC = MRI->getRegClass(CP.getDstReg());
3904 << TRI->getRegClassName(MRI->getRegClass(Re
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H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
H A DAggressiveAntiDepBreaker.cpp409 RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
493 RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp699 const TargetRegisterClass *RC = MRI->getRegClass(R);
842 const TargetRegisterClass *RC = MRI->getRegClass(DR);
1000 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
H A DHexagonStoreWidening.cpp444 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);
H A DHexagonConstPropagation.cpp1954 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
2210 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
2362 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
2867 const TargetRegisterClass *RC = MRI->getRegClass(R);
2992 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3021 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3058 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3090 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp256 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
643 const TargetRegisterClass *DestRC = MRI->getRegClass(DestReg);
647 const TargetRegisterClass * SrcRC = MRI->getRegClass(SrcReg);
864 TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
869 const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg);
H A DAMDGPUMachineCFGStructurizer.cpp1409 MRI->createVirtualRegister(MRI->getRegClass(DestReg));
1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2177 MRI->getRegClass(CurrentBackedgeReg);
2314 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2451 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest);
2741 MRI->createVirtualRegister(MRI->getRegClass(InReg));
2742 Register NewInReg = MRI->createVirtualRegister(MRI->getRegClass(InReg));
H A DR600MachineScheduler.cpp215 return MRI->getRegClass(Reg) == RC;
H A DSIFormMemoryClauses.cpp162 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp425 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
426 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
427 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp288 MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI, MF));
H A DARMBaseRegisterInfo.cpp646 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
815 TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp88 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp895 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
903 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
911 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
921 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
929 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
937 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
945 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
956 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
964 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
972 return RegIdx.RegInfo->getRegClass(ClassI
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp162 return RC->hasSubClassEq(MRI->getRegClass(Reg));
898 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp396 TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent())));
566 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI,
H A DX86FlagsCopyLowering.cpp985 auto &SetBRC = *MRI->getRegClass(SetBI.getOperand(0).getReg());
992 auto &OrigRC = *MRI->getRegClass(Reg);

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