1284677Sdim//===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===// 2284677Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6284677Sdim// 7284677Sdim//===----------------------------------------------------------------------===// 8284677Sdim// 9284677Sdim/// \file 10341825Sdim/// R600 Machine Scheduler interface 11284677Sdim// 12284677Sdim//===----------------------------------------------------------------------===// 13284677Sdim 14284677Sdim#include "R600MachineScheduler.h" 15321369Sdim#include "AMDGPUSubtarget.h" 16309124Sdim#include "R600InstrInfo.h" 17341825Sdim#include "MCTargetDesc/AMDGPUMCTargetDesc.h" 18284677Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 19321369Sdim#include "llvm/IR/LegacyPassManager.h" 20284677Sdim#include "llvm/Pass.h" 21284677Sdim#include "llvm/Support/raw_ostream.h" 22284677Sdim 23284677Sdimusing namespace llvm; 24284677Sdim 25321369Sdim#define DEBUG_TYPE "machine-scheduler" 26284677Sdim 27284677Sdimvoid R600SchedStrategy::initialize(ScheduleDAGMI *dag) { 28284677Sdim assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); 29284677Sdim DAG = static_cast<ScheduleDAGMILive*>(dag); 30309124Sdim const R600Subtarget &ST = DAG->MF.getSubtarget<R600Subtarget>(); 31284677Sdim TII = static_cast<const R600InstrInfo*>(DAG->TII); 32284677Sdim TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); 33284677Sdim VLIW5 = !ST.hasCaymanISA(); 34284677Sdim MRI = &DAG->MRI; 35284677Sdim CurInstKind = IDOther; 36284677Sdim CurEmitted = 0; 37284677Sdim OccupedSlotsMask = 31; 38284677Sdim InstKindLimit[IDAlu] = TII->getMaxAlusPerClause(); 39284677Sdim InstKindLimit[IDOther] = 32; 40284677Sdim InstKindLimit[IDFetch] = ST.getTexVTXClauseSize(); 41284677Sdim AluInstCount = 0; 42284677Sdim FetchInstCount = 0; 43284677Sdim} 44284677Sdim 45284677Sdimvoid R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc, 46284677Sdim std::vector<SUnit *> &QDst) 47284677Sdim{ 48284677Sdim QDst.insert(QDst.end(), QSrc.begin(), QSrc.end()); 49284677Sdim QSrc.clear(); 50284677Sdim} 51284677Sdim 52309124Sdimstatic unsigned getWFCountLimitedByGPR(unsigned GPRCount) { 53284677Sdim assert (GPRCount && "GPRCount cannot be 0"); 54284677Sdim return 248 / GPRCount; 55284677Sdim} 56284677Sdim 57284677SdimSUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { 58284677Sdim SUnit *SU = nullptr; 59284677Sdim NextInstKind = IDOther; 60284677Sdim 61284677Sdim IsTopNode = false; 62284677Sdim 63284677Sdim // check if we might want to switch current clause type 64284677Sdim bool AllowSwitchToAlu = (CurEmitted >= InstKindLimit[CurInstKind]) || 65284677Sdim (Available[CurInstKind].empty()); 66284677Sdim bool AllowSwitchFromAlu = (CurEmitted >= InstKindLimit[CurInstKind]) && 67284677Sdim (!Available[IDFetch].empty() || !Available[IDOther].empty()); 68284677Sdim 69284677Sdim if (CurInstKind == IDAlu && !Available[IDFetch].empty()) { 70284677Sdim // We use the heuristic provided by AMD Accelerated Parallel Processing 71284677Sdim // OpenCL Programming Guide : 72284677Sdim // The approx. number of WF that allows TEX inst to hide ALU inst is : 73284677Sdim // 500 (cycles for TEX) / (AluFetchRatio * 8 (cycles for ALU)) 74284677Sdim float ALUFetchRationEstimate = 75284677Sdim (AluInstCount + AvailablesAluCount() + Pending[IDAlu].size()) / 76284677Sdim (FetchInstCount + Available[IDFetch].size()); 77284677Sdim if (ALUFetchRationEstimate == 0) { 78284677Sdim AllowSwitchFromAlu = true; 79284677Sdim } else { 80284677Sdim unsigned NeededWF = 62.5f / ALUFetchRationEstimate; 81341825Sdim LLVM_DEBUG(dbgs() << NeededWF << " approx. Wavefronts Required\n"); 82284677Sdim // We assume the local GPR requirements to be "dominated" by the requirement 83284677Sdim // of the TEX clause (which consumes 128 bits regs) ; ALU inst before and 84284677Sdim // after TEX are indeed likely to consume or generate values from/for the 85284677Sdim // TEX clause. 86284677Sdim // Available[IDFetch].size() * 2 : GPRs required in the Fetch clause 87284677Sdim // We assume that fetch instructions are either TnXYZW = TEX TnXYZW (need 88284677Sdim // one GPR) or TmXYZW = TnXYZW (need 2 GPR). 89284677Sdim // (TODO : use RegisterPressure) 90284677Sdim // If we are going too use too many GPR, we flush Fetch instruction to lower 91284677Sdim // register pressure on 128 bits regs. 92284677Sdim unsigned NearRegisterRequirement = 2 * Available[IDFetch].size(); 93284677Sdim if (NeededWF > getWFCountLimitedByGPR(NearRegisterRequirement)) 94284677Sdim AllowSwitchFromAlu = true; 95284677Sdim } 96284677Sdim } 97284677Sdim 98284677Sdim if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || 99284677Sdim (!AllowSwitchFromAlu && CurInstKind == IDAlu))) { 100284677Sdim // try to pick ALU 101284677Sdim SU = pickAlu(); 102284677Sdim if (!SU && !PhysicalRegCopy.empty()) { 103284677Sdim SU = PhysicalRegCopy.front(); 104284677Sdim PhysicalRegCopy.erase(PhysicalRegCopy.begin()); 105284677Sdim } 106284677Sdim if (SU) { 107284677Sdim if (CurEmitted >= InstKindLimit[IDAlu]) 108284677Sdim CurEmitted = 0; 109284677Sdim NextInstKind = IDAlu; 110284677Sdim } 111284677Sdim } 112284677Sdim 113284677Sdim if (!SU) { 114284677Sdim // try to pick FETCH 115284677Sdim SU = pickOther(IDFetch); 116284677Sdim if (SU) 117284677Sdim NextInstKind = IDFetch; 118284677Sdim } 119284677Sdim 120284677Sdim // try to pick other 121284677Sdim if (!SU) { 122284677Sdim SU = pickOther(IDOther); 123284677Sdim if (SU) 124284677Sdim NextInstKind = IDOther; 125284677Sdim } 126284677Sdim 127341825Sdim LLVM_DEBUG(if (SU) { 128341825Sdim dbgs() << " ** Pick node **\n"; 129344779Sdim DAG->dumpNode(*SU); 130341825Sdim } else { 131341825Sdim dbgs() << "NO NODE \n"; 132341825Sdim for (unsigned i = 0; i < DAG->SUnits.size(); i++) { 133341825Sdim const SUnit &S = DAG->SUnits[i]; 134341825Sdim if (!S.isScheduled) 135344779Sdim DAG->dumpNode(S); 136341825Sdim } 137341825Sdim }); 138284677Sdim 139284677Sdim return SU; 140284677Sdim} 141284677Sdim 142284677Sdimvoid R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { 143284677Sdim if (NextInstKind != CurInstKind) { 144341825Sdim LLVM_DEBUG(dbgs() << "Instruction Type Switch\n"); 145284677Sdim if (NextInstKind != IDAlu) 146284677Sdim OccupedSlotsMask |= 31; 147284677Sdim CurEmitted = 0; 148284677Sdim CurInstKind = NextInstKind; 149284677Sdim } 150284677Sdim 151284677Sdim if (CurInstKind == IDAlu) { 152284677Sdim AluInstCount ++; 153284677Sdim switch (getAluKind(SU)) { 154284677Sdim case AluT_XYZW: 155284677Sdim CurEmitted += 4; 156284677Sdim break; 157284677Sdim case AluDiscarded: 158284677Sdim break; 159284677Sdim default: { 160284677Sdim ++CurEmitted; 161284677Sdim for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), 162284677Sdim E = SU->getInstr()->operands_end(); It != E; ++It) { 163284677Sdim MachineOperand &MO = *It; 164341825Sdim if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) 165284677Sdim ++CurEmitted; 166284677Sdim } 167284677Sdim } 168284677Sdim } 169284677Sdim } else { 170284677Sdim ++CurEmitted; 171284677Sdim } 172284677Sdim 173341825Sdim LLVM_DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n"); 174284677Sdim 175284677Sdim if (CurInstKind != IDFetch) { 176284677Sdim MoveUnits(Pending[IDFetch], Available[IDFetch]); 177284677Sdim } else 178284677Sdim FetchInstCount++; 179284677Sdim} 180284677Sdim 181284677Sdimstatic bool 182284677SdimisPhysicalRegCopy(MachineInstr *MI) { 183341825Sdim if (MI->getOpcode() != R600::COPY) 184284677Sdim return false; 185284677Sdim 186360784Sdim return !Register::isVirtualRegister(MI->getOperand(1).getReg()); 187284677Sdim} 188284677Sdim 189284677Sdimvoid R600SchedStrategy::releaseTopNode(SUnit *SU) { 190344779Sdim LLVM_DEBUG(dbgs() << "Top Releasing "; DAG->dumpNode(*SU)); 191284677Sdim} 192284677Sdim 193284677Sdimvoid R600SchedStrategy::releaseBottomNode(SUnit *SU) { 194344779Sdim LLVM_DEBUG(dbgs() << "Bottom Releasing "; DAG->dumpNode(*SU)); 195284677Sdim if (isPhysicalRegCopy(SU->getInstr())) { 196284677Sdim PhysicalRegCopy.push_back(SU); 197284677Sdim return; 198284677Sdim } 199284677Sdim 200284677Sdim int IK = getInstKind(SU); 201284677Sdim 202284677Sdim // There is no export clause, we can schedule one as soon as its ready 203284677Sdim if (IK == IDOther) 204284677Sdim Available[IDOther].push_back(SU); 205284677Sdim else 206284677Sdim Pending[IK].push_back(SU); 207284677Sdim 208284677Sdim} 209284677Sdim 210284677Sdimbool R600SchedStrategy::regBelongsToClass(unsigned Reg, 211284677Sdim const TargetRegisterClass *RC) const { 212360784Sdim if (!Register::isVirtualRegister(Reg)) { 213284677Sdim return RC->contains(Reg); 214284677Sdim } else { 215284677Sdim return MRI->getRegClass(Reg) == RC; 216284677Sdim } 217284677Sdim} 218284677Sdim 219284677SdimR600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const { 220284677Sdim MachineInstr *MI = SU->getInstr(); 221284677Sdim 222309124Sdim if (TII->isTransOnly(*MI)) 223284677Sdim return AluTrans; 224284677Sdim 225309124Sdim switch (MI->getOpcode()) { 226341825Sdim case R600::PRED_X: 227309124Sdim return AluPredX; 228341825Sdim case R600::INTERP_PAIR_XY: 229341825Sdim case R600::INTERP_PAIR_ZW: 230341825Sdim case R600::INTERP_VEC_LOAD: 231341825Sdim case R600::DOT_4: 232309124Sdim return AluT_XYZW; 233341825Sdim case R600::COPY: 234309124Sdim if (MI->getOperand(1).isUndef()) { 235309124Sdim // MI will become a KILL, don't considers it in scheduling 236309124Sdim return AluDiscarded; 237284677Sdim } 238344779Sdim break; 239309124Sdim default: 240309124Sdim break; 241309124Sdim } 242284677Sdim 243309124Sdim // Does the instruction take a whole IG ? 244309124Sdim // XXX: Is it possible to add a helper function in R600InstrInfo that can 245309124Sdim // be used here and in R600PacketizerList::isSoloInstruction() ? 246309124Sdim if(TII->isVector(*MI) || 247309124Sdim TII->isCubeOp(MI->getOpcode()) || 248309124Sdim TII->isReductionOp(MI->getOpcode()) || 249341825Sdim MI->getOpcode() == R600::GROUP_BARRIER) { 250309124Sdim return AluT_XYZW; 251309124Sdim } 252284677Sdim 253309124Sdim if (TII->isLDSInstr(MI->getOpcode())) { 254309124Sdim return AluT_X; 255309124Sdim } 256284677Sdim 257309124Sdim // Is the result already assigned to a channel ? 258309124Sdim unsigned DestSubReg = MI->getOperand(0).getSubReg(); 259309124Sdim switch (DestSubReg) { 260341825Sdim case R600::sub0: 261309124Sdim return AluT_X; 262341825Sdim case R600::sub1: 263309124Sdim return AluT_Y; 264341825Sdim case R600::sub2: 265309124Sdim return AluT_Z; 266341825Sdim case R600::sub3: 267309124Sdim return AluT_W; 268309124Sdim default: 269309124Sdim break; 270309124Sdim } 271284677Sdim 272309124Sdim // Is the result already member of a X/Y/Z/W class ? 273360784Sdim Register DestReg = MI->getOperand(0).getReg(); 274341825Sdim if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || 275341825Sdim regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) 276309124Sdim return AluT_X; 277341825Sdim if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) 278309124Sdim return AluT_Y; 279341825Sdim if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) 280309124Sdim return AluT_Z; 281341825Sdim if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) 282309124Sdim return AluT_W; 283341825Sdim if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) 284309124Sdim return AluT_XYZW; 285284677Sdim 286309124Sdim // LDS src registers cannot be used in the Trans slot. 287309124Sdim if (TII->readsLDSSrcReg(*MI)) 288309124Sdim return AluT_XYZW; 289284677Sdim 290309124Sdim return AluAny; 291284677Sdim} 292284677Sdim 293284677Sdimint R600SchedStrategy::getInstKind(SUnit* SU) { 294284677Sdim int Opcode = SU->getInstr()->getOpcode(); 295284677Sdim 296284677Sdim if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode)) 297284677Sdim return IDFetch; 298284677Sdim 299284677Sdim if (TII->isALUInstr(Opcode)) { 300284677Sdim return IDAlu; 301284677Sdim } 302284677Sdim 303284677Sdim switch (Opcode) { 304341825Sdim case R600::PRED_X: 305341825Sdim case R600::COPY: 306341825Sdim case R600::CONST_COPY: 307341825Sdim case R600::INTERP_PAIR_XY: 308341825Sdim case R600::INTERP_PAIR_ZW: 309341825Sdim case R600::INTERP_VEC_LOAD: 310341825Sdim case R600::DOT_4: 311284677Sdim return IDAlu; 312284677Sdim default: 313284677Sdim return IDOther; 314284677Sdim } 315284677Sdim} 316284677Sdim 317284677SdimSUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { 318284677Sdim if (Q.empty()) 319284677Sdim return nullptr; 320284677Sdim for (std::vector<SUnit *>::reverse_iterator It = Q.rbegin(), E = Q.rend(); 321284677Sdim It != E; ++It) { 322284677Sdim SUnit *SU = *It; 323284677Sdim InstructionsGroupCandidate.push_back(SU->getInstr()); 324309124Sdim if (TII->fitsConstReadLimitations(InstructionsGroupCandidate) && 325309124Sdim (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { 326284677Sdim InstructionsGroupCandidate.pop_back(); 327284677Sdim Q.erase((It + 1).base()); 328284677Sdim return SU; 329284677Sdim } else { 330284677Sdim InstructionsGroupCandidate.pop_back(); 331284677Sdim } 332284677Sdim } 333284677Sdim return nullptr; 334284677Sdim} 335284677Sdim 336284677Sdimvoid R600SchedStrategy::LoadAlu() { 337284677Sdim std::vector<SUnit *> &QSrc = Pending[IDAlu]; 338284677Sdim for (unsigned i = 0, e = QSrc.size(); i < e; ++i) { 339284677Sdim AluKind AK = getAluKind(QSrc[i]); 340284677Sdim AvailableAlus[AK].push_back(QSrc[i]); 341284677Sdim } 342284677Sdim QSrc.clear(); 343284677Sdim} 344284677Sdim 345284677Sdimvoid R600SchedStrategy::PrepareNextSlot() { 346341825Sdim LLVM_DEBUG(dbgs() << "New Slot\n"); 347284677Sdim assert (OccupedSlotsMask && "Slot wasn't filled"); 348284677Sdim OccupedSlotsMask = 0; 349341825Sdim// if (HwGen == AMDGPUSubtarget::NORTHERN_ISLANDS) 350284677Sdim// OccupedSlotsMask |= 16; 351284677Sdim InstructionsGroupCandidate.clear(); 352284677Sdim LoadAlu(); 353284677Sdim} 354284677Sdim 355284677Sdimvoid R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) { 356341825Sdim int DstIndex = TII->getOperandIdx(MI->getOpcode(), R600::OpName::dst); 357284677Sdim if (DstIndex == -1) { 358284677Sdim return; 359284677Sdim } 360360784Sdim Register DestReg = MI->getOperand(DstIndex).getReg(); 361284677Sdim // PressureRegister crashes if an operand is def and used in the same inst 362284677Sdim // and we try to constraint its regclass 363284677Sdim for (MachineInstr::mop_iterator It = MI->operands_begin(), 364284677Sdim E = MI->operands_end(); It != E; ++It) { 365284677Sdim MachineOperand &MO = *It; 366284677Sdim if (MO.isReg() && !MO.isDef() && 367284677Sdim MO.getReg() == DestReg) 368284677Sdim return; 369284677Sdim } 370284677Sdim // Constrains the regclass of DestReg to assign it to Slot 371284677Sdim switch (Slot) { 372284677Sdim case 0: 373341825Sdim MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); 374284677Sdim break; 375284677Sdim case 1: 376341825Sdim MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass); 377284677Sdim break; 378284677Sdim case 2: 379341825Sdim MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass); 380284677Sdim break; 381284677Sdim case 3: 382341825Sdim MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass); 383284677Sdim break; 384284677Sdim } 385284677Sdim} 386284677Sdim 387284677SdimSUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot, bool AnyAlu) { 388284677Sdim static const AluKind IndexToID[] = {AluT_X, AluT_Y, AluT_Z, AluT_W}; 389284677Sdim SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); 390284677Sdim if (SlotedSU) 391284677Sdim return SlotedSU; 392284677Sdim SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); 393284677Sdim if (UnslotedSU) 394284677Sdim AssignSlot(UnslotedSU->getInstr(), Slot); 395284677Sdim return UnslotedSU; 396284677Sdim} 397284677Sdim 398284677Sdimunsigned R600SchedStrategy::AvailablesAluCount() const { 399284677Sdim return AvailableAlus[AluAny].size() + AvailableAlus[AluT_XYZW].size() + 400284677Sdim AvailableAlus[AluT_X].size() + AvailableAlus[AluT_Y].size() + 401284677Sdim AvailableAlus[AluT_Z].size() + AvailableAlus[AluT_W].size() + 402284677Sdim AvailableAlus[AluTrans].size() + AvailableAlus[AluDiscarded].size() + 403284677Sdim AvailableAlus[AluPredX].size(); 404284677Sdim} 405284677Sdim 406284677SdimSUnit* R600SchedStrategy::pickAlu() { 407284677Sdim while (AvailablesAluCount() || !Pending[IDAlu].empty()) { 408284677Sdim if (!OccupedSlotsMask) { 409284677Sdim // Bottom up scheduling : predX must comes first 410284677Sdim if (!AvailableAlus[AluPredX].empty()) { 411284677Sdim OccupedSlotsMask |= 31; 412284677Sdim return PopInst(AvailableAlus[AluPredX], false); 413284677Sdim } 414284677Sdim // Flush physical reg copies (RA will discard them) 415284677Sdim if (!AvailableAlus[AluDiscarded].empty()) { 416284677Sdim OccupedSlotsMask |= 31; 417284677Sdim return PopInst(AvailableAlus[AluDiscarded], false); 418284677Sdim } 419284677Sdim // If there is a T_XYZW alu available, use it 420284677Sdim if (!AvailableAlus[AluT_XYZW].empty()) { 421284677Sdim OccupedSlotsMask |= 15; 422284677Sdim return PopInst(AvailableAlus[AluT_XYZW], false); 423284677Sdim } 424284677Sdim } 425284677Sdim bool TransSlotOccuped = OccupedSlotsMask & 16; 426284677Sdim if (!TransSlotOccuped && VLIW5) { 427284677Sdim if (!AvailableAlus[AluTrans].empty()) { 428284677Sdim OccupedSlotsMask |= 16; 429284677Sdim return PopInst(AvailableAlus[AluTrans], false); 430284677Sdim } 431284677Sdim SUnit *SU = AttemptFillSlot(3, true); 432284677Sdim if (SU) { 433284677Sdim OccupedSlotsMask |= 16; 434284677Sdim return SU; 435284677Sdim } 436284677Sdim } 437284677Sdim for (int Chan = 3; Chan > -1; --Chan) { 438284677Sdim bool isOccupied = OccupedSlotsMask & (1 << Chan); 439284677Sdim if (!isOccupied) { 440284677Sdim SUnit *SU = AttemptFillSlot(Chan, false); 441284677Sdim if (SU) { 442284677Sdim OccupedSlotsMask |= (1 << Chan); 443284677Sdim InstructionsGroupCandidate.push_back(SU->getInstr()); 444284677Sdim return SU; 445284677Sdim } 446284677Sdim } 447284677Sdim } 448284677Sdim PrepareNextSlot(); 449284677Sdim } 450284677Sdim return nullptr; 451284677Sdim} 452284677Sdim 453284677SdimSUnit* R600SchedStrategy::pickOther(int QID) { 454284677Sdim SUnit *SU = nullptr; 455284677Sdim std::vector<SUnit *> &AQ = Available[QID]; 456284677Sdim 457284677Sdim if (AQ.empty()) { 458284677Sdim MoveUnits(Pending[QID], AQ); 459284677Sdim } 460284677Sdim if (!AQ.empty()) { 461284677Sdim SU = AQ.back(); 462341825Sdim AQ.pop_back(); 463284677Sdim } 464284677Sdim return SU; 465284677Sdim} 466