/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 139 const TargetRegisterClass *RC = MRI->getRegClass(R); 336 if (MRI->getRegClass(PR.R) != PredRC) 435 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); 479 if (MRI->getRegClass(DR.R) != PredRC) 481 if (MRI->getRegClass(SR.R) != PredRC)
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H A D | HexagonSplitDouble.cpp | 228 if (MRI->getRegClass(R) == DoubleRC) 266 if (MRI->getRegClass(T) != DoubleRC) 503 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass); 517 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC) 519 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC) 539 if (MRI->getRegClass(R) == DoubleRC) 610 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) { 676 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); 1006 if (MRI->getRegClass(DstR) == DoubleRC) { 1110 if (MRI->getRegClass( [all...] |
H A D | HexagonBitSimplify.cpp | 407 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); 437 auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg()); 899 auto *RC = MRI.getRegClass(RR.Reg); 1479 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); 1552 if (FRC != MRI.getRegClass(R)) 1567 if (MRI.getRegClass(R) != &Hexagon::DoubleRegsRegClass) 1686 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); 1696 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); 1876 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); 2227 unsigned SRC = MRI.getRegClass( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); 254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 373 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); 438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); 487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
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H A D | LiveRangeEdit.cpp | 35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 472 << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
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H A D | OptimizePHIs.cpp | 181 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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H A D | MIRCanonicalizerPass.cpp | 334 if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
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H A D | ModuloSchedule.cpp | 548 const TargetRegisterClass *RC = MRI.getRegClass(Def); 664 const TargetRegisterClass *RC = MRI.getRegClass(Def); 812 SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def)); 1033 const TargetRegisterClass *RC = MRI.getRegClass(reg); 1184 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); 1232 MRI.getRegClass(MI.getOperand(0).getReg())); 1428 LoopReg = phi(LoopReg, *DefaultI++, MRI.getRegClass(Reg)); 1436 auto RC = MRI.getRegClass(Reg); 1476 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue())); 1483 RC = MRI.getRegClass(LoopRe [all...] |
H A D | TailDuplicator.cpp | 248 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { 355 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 398 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 410 auto *OrigRC = MRI->getRegClass(Reg); 411 auto *MappedRC = MRI->getRegClass(VI->second.Reg);
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H A D | MachineRegisterInfo.cpp | 88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); 124 const TargetRegisterClass *OldRC = getRegClass(Reg); 502 const TargetRegisterClass &TRC = *getRegClass(Reg);
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H A D | VirtRegMap.cpp | 123 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); 144 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; 152 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 488 ? MRI.getRegClass(Reg) 763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); 829 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); 830 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && 2135 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); 2136 assert(MRI.getRegClass(FalseReg) == RC); 2149 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); 2150 assert(MRI.getRegClass(FalseReg) == RC); 2177 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); 2383 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src [all...] |
H A D | SIPreAllocateWWMRegs.cpp | 107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
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H A D | SIInstrInfo.h | 818 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; 829 getRegClass(MO.getReg()), SubReg)) >= 32 && 1030 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum, 1036 return RI.getRegClass(TID.OpInfo[OpNum].RegClass); 1057 auto *RC = MRI.getRegClass(P.Reg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.cpp | 1268 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || 1269 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || 1270 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) 1272 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || 1273 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || 1274 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) 1276 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || 1277 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || 1278 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) 1291 if (MRI.getRegClass(AArch6 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
H A D | MIParser.h | 141 const TargetRegisterClass *getRegClass(StringRef Name);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ConditionalCompares.cpp | 635 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); 644 TII->getRegClass(MCID, 1, TRI, *MF)); 691 TII->getRegClass(MCID, 0, TRI, *MF)); 694 TII->getRegClass(MCID, 1, TRI, *MF));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != 366 MRI->getRegClass(DefMI->getOperand(0).getReg())) 434 if (MRI->getRegClass(First.getOperand(0).getReg()) != 435 MRI->getRegClass(Last.getOperand(0).getReg()))
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H A D | X86DomainReassignment.cpp | 186 TII->getRegClass(TII->get(DstOpcode), 0, MRI->getTargetRegisterInfo(), 247 RegDomain OpDomain = getDomain(MRI->getRegClass(MO.getReg()), 445 RegDomain RD = getDomain(MRI->getRegClass(Reg), MRI->getTargetRegisterInfo()); 511 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); 757 if (!isGPR(MRI->getRegClass(Reg)))
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 54 return RC->hasSubClassEq(MRI.getRegClass(Reg));
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H A D | PPCFastISel.cpp | 469 (ResultReg ? MRI.getRegClass(ResultReg) : 613 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; 629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); 867 auto RC1 = MRI.getRegClass(SrcReg1); 868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; 990 auto RC = MRI.getRegClass(SrcReg); 1177 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; 1217 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg); 1227 auto RC = MRI.getRegClass(SrcReg); 1282 (AssignedReg ? MRI.getRegClass(AssignedRe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenTarget.h | 122 return *getRegBank().getRegClass(R);
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H A D | RegisterBankEmitter.cpp | 67 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMCInstLower.cpp | 242 Returns.push_back(getType(MRI.getRegClass(MO.getReg()))); 245 Params.push_back(getType(MRI.getRegClass(MO.getReg())));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 421 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || 422 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg))
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