Searched refs:getRegClass (Results 26 - 50 of 185) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp139 const TargetRegisterClass *RC = MRI->getRegClass(R);
336 if (MRI->getRegClass(PR.R) != PredRC)
435 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R);
479 if (MRI->getRegClass(DR.R) != PredRC)
481 if (MRI->getRegClass(SR.R) != PredRC)
H A DHexagonSplitDouble.cpp228 if (MRI->getRegClass(R) == DoubleRC)
266 if (MRI->getRegClass(T) != DoubleRC)
503 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
517 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC)
519 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC)
539 if (MRI->getRegClass(R) == DoubleRC)
610 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
676 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
1006 if (MRI->getRegClass(DstR) == DoubleRC) {
1110 if (MRI->getRegClass(
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H A DHexagonBitSimplify.cpp407 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
437 auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
899 auto *RC = MRI.getRegClass(RR.Reg);
1479 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
1552 if (FRC != MRI.getRegClass(R))
1567 if (MRI.getRegClass(R) != &Hexagon::DoubleRegsRegClass)
1686 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
1696 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
1876 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF);
2227 unsigned SRC = MRI.getRegClass(
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
373 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
H A DLiveRangeEdit.cpp35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
472 << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
H A DOptimizePHIs.cpp181 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
H A DMIRCanonicalizerPass.cpp334 if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
H A DModuloSchedule.cpp548 const TargetRegisterClass *RC = MRI.getRegClass(Def);
664 const TargetRegisterClass *RC = MRI.getRegClass(Def);
812 SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def));
1033 const TargetRegisterClass *RC = MRI.getRegClass(reg);
1184 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg));
1232 MRI.getRegClass(MI.getOperand(0).getReg()));
1428 LoopReg = phi(LoopReg, *DefaultI++, MRI.getRegClass(Reg));
1436 auto RC = MRI.getRegClass(Reg);
1476 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue()));
1483 RC = MRI.getRegClass(LoopRe
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H A DTailDuplicator.cpp248 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
355 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
398 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
410 auto *OrigRC = MRI->getRegClass(Reg);
411 auto *MappedRC = MRI->getRegClass(VI->second.Reg);
H A DMachineRegisterInfo.cpp88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
124 const TargetRegisterClass *OldRC = getRegClass(Reg);
502 const TargetRegisterClass &TRC = *getRegClass(Reg);
H A DVirtRegMap.cpp123 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
144 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
152 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp488 ? MRI.getRegClass(Reg)
763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
829 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
830 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
2135 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2136 assert(MRI.getRegClass(FalseReg) == RC);
2149 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2150 assert(MRI.getRegClass(FalseReg) == RC);
2177 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2383 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src
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H A DSIPreAllocateWWMRegs.cpp107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
H A DSIInstrInfo.h818 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
829 getRegClass(MO.getReg()), SubReg)) >= 32 &&
1030 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1036 return RI.getRegClass(TID.OpInfo[OpNum].RegClass);
1057 auto *RC = MRI.getRegClass(P.Reg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1268 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1269 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1270 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1272 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1273 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1274 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1276 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1277 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1278 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1291 if (MRI.getRegClass(AArch6
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h141 const TargetRegisterClass *getRegClass(StringRef Name);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp635 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
644 TII->getRegClass(MCID, 1, TRI, *MF));
691 TII->getRegClass(MCID, 0, TRI, *MF));
694 TII->getRegClass(MCID, 1, TRI, *MF));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=
366 MRI->getRegClass(DefMI->getOperand(0).getReg()))
434 if (MRI->getRegClass(First.getOperand(0).getReg()) !=
435 MRI->getRegClass(Last.getOperand(0).getReg()))
H A DX86DomainReassignment.cpp186 TII->getRegClass(TII->get(DstOpcode), 0, MRI->getTargetRegisterInfo(),
247 RegDomain OpDomain = getDomain(MRI->getRegClass(MO.getReg()),
445 RegDomain RD = getDomain(MRI->getRegClass(Reg), MRI->getTargetRegisterInfo());
511 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain));
757 if (!isGPR(MRI->getRegClass(Reg)))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp54 return RC->hasSubClassEq(MRI.getRegClass(Reg));
H A DPPCFastISel.cpp469 (ResultReg ? MRI.getRegClass(ResultReg) :
613 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
867 auto RC1 = MRI.getRegClass(SrcReg1);
868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
990 auto RC = MRI.getRegClass(SrcReg);
1177 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1217 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1227 auto RC = MRI.getRegClass(SrcReg);
1282 (AssignedReg ? MRI.getRegClass(AssignedRe
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.h122 return *getRegBank().getRegClass(R);
H A DRegisterBankEmitter.cpp67 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp242 Returns.push_back(getType(MRI.getRegClass(MO.getReg())));
245 Params.push_back(getType(MRI.getRegClass(MO.getReg())));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp421 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
422 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg))

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