1//===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the function that parses the machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
14#define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
15
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/StringMap.h"
18#include "llvm/CodeGen/MachineMemOperand.h"
19#include "llvm/Support/Allocator.h"
20
21namespace llvm {
22
23class MachineBasicBlock;
24class MachineFunction;
25class MDNode;
26class RegisterBank;
27struct SlotMapping;
28class SMDiagnostic;
29class SourceMgr;
30class StringRef;
31class TargetRegisterClass;
32class TargetSubtargetInfo;
33
34struct VRegInfo {
35  enum uint8_t {
36    UNKNOWN, NORMAL, GENERIC, REGBANK
37  } Kind = UNKNOWN;
38  bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
39  union {
40    const TargetRegisterClass *RC;
41    const RegisterBank *RegBank;
42  } D;
43  unsigned VReg;
44  unsigned PreferredReg = 0;
45};
46
47using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
48using Name2RegBankMap = StringMap<const RegisterBank *>;
49
50struct PerTargetMIParsingState {
51private:
52  const TargetSubtargetInfo &Subtarget;
53
54  /// Maps from instruction names to op codes.
55  StringMap<unsigned> Names2InstrOpCodes;
56
57  /// Maps from register names to registers.
58  StringMap<unsigned> Names2Regs;
59
60  /// Maps from register mask names to register masks.
61  StringMap<const uint32_t *> Names2RegMasks;
62
63  /// Maps from subregister names to subregister indices.
64  StringMap<unsigned> Names2SubRegIndices;
65
66  /// Maps from target index names to target indices.
67  StringMap<int> Names2TargetIndices;
68
69  /// Maps from direct target flag names to the direct target flag values.
70  StringMap<unsigned> Names2DirectTargetFlags;
71
72  /// Maps from direct target flag names to the bitmask target flag values.
73  StringMap<unsigned> Names2BitmaskTargetFlags;
74
75  /// Maps from MMO target flag names to MMO target flag values.
76  StringMap<MachineMemOperand::Flags> Names2MMOTargetFlags;
77
78  /// Maps from register class names to register classes.
79  Name2RegClassMap Names2RegClasses;
80
81  /// Maps from register bank names to register banks.
82  Name2RegBankMap Names2RegBanks;
83
84  void initNames2InstrOpCodes();
85  void initNames2Regs();
86  void initNames2RegMasks();
87  void initNames2SubRegIndices();
88  void initNames2TargetIndices();
89  void initNames2DirectTargetFlags();
90  void initNames2BitmaskTargetFlags();
91  void initNames2MMOTargetFlags();
92
93  void initNames2RegClasses();
94  void initNames2RegBanks();
95
96public:
97  /// Try to convert an instruction name to an opcode. Return true if the
98  /// instruction name is invalid.
99  bool parseInstrName(StringRef InstrName, unsigned &OpCode);
100
101  /// Try to convert a register name to a register number. Return true if the
102  /// register name is invalid.
103  bool getRegisterByName(StringRef RegName, unsigned &Reg);
104
105  /// Check if the given identifier is a name of a register mask.
106  ///
107  /// Return null if the identifier isn't a register mask.
108  const uint32_t *getRegMask(StringRef Identifier);
109
110  /// Check if the given identifier is a name of a subregister index.
111  ///
112  /// Return 0 if the name isn't a subregister index class.
113  unsigned getSubRegIndex(StringRef Name);
114
115  /// Try to convert a name of target index to the corresponding target index.
116  ///
117  /// Return true if the name isn't a name of a target index.
118  bool getTargetIndex(StringRef Name, int &Index);
119
120  /// Try to convert a name of a direct target flag to the corresponding
121  /// target flag.
122  ///
123  /// Return true if the name isn't a name of a direct flag.
124  bool getDirectTargetFlag(StringRef Name, unsigned &Flag);
125
126  /// Try to convert a name of a bitmask target flag to the corresponding
127  /// target flag.
128  ///
129  /// Return true if the name isn't a name of a bitmask target flag.
130  bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag);
131
132  /// Try to convert a name of a MachineMemOperand target flag to the
133  /// corresponding target flag.
134  ///
135  /// Return true if the name isn't a name of a target MMO flag.
136  bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag);
137
138  /// Check if the given identifier is a name of a register class.
139  ///
140  /// Return null if the name isn't a register class.
141  const TargetRegisterClass *getRegClass(StringRef Name);
142
143  /// Check if the given identifier is a name of a register bank.
144  ///
145  /// Return null if the name isn't a register bank.
146  const RegisterBank *getRegBank(StringRef Name);
147
148  PerTargetMIParsingState(const TargetSubtargetInfo &STI)
149    : Subtarget(STI) {
150    initNames2RegClasses();
151    initNames2RegBanks();
152  }
153
154  ~PerTargetMIParsingState() = default;
155
156  void setTarget(const TargetSubtargetInfo &NewSubtarget);
157};
158
159struct PerFunctionMIParsingState {
160  BumpPtrAllocator Allocator;
161  MachineFunction &MF;
162  SourceMgr *SM;
163  const SlotMapping &IRSlots;
164  PerTargetMIParsingState &Target;
165
166  DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
167  DenseMap<unsigned, VRegInfo *> VRegInfos;
168  StringMap<VRegInfo *> VRegInfosNamed;
169  DenseMap<unsigned, int> FixedStackObjectSlots;
170  DenseMap<unsigned, int> StackObjectSlots;
171  DenseMap<unsigned, unsigned> ConstantPoolSlots;
172  DenseMap<unsigned, unsigned> JumpTableSlots;
173
174  /// Maps from slot numbers to function's unnamed values.
175  DenseMap<unsigned, const Value *> Slots2Values;
176
177  PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
178                            const SlotMapping &IRSlots,
179                            PerTargetMIParsingState &Target);
180
181  VRegInfo &getVRegInfo(unsigned Num);
182  VRegInfo &getVRegInfoNamed(StringRef RegName);
183  const Value *getIRValue(unsigned Slot);
184};
185
186/// Parse the machine basic block definitions, and skip the machine
187/// instructions.
188///
189/// This function runs the first parsing pass on the machine function's body.
190/// It parses only the machine basic block definitions and creates the machine
191/// basic blocks in the given machine function.
192///
193/// The machine instructions aren't parsed during the first pass because all
194/// the machine basic blocks aren't defined yet - this makes it impossible to
195/// resolve the machine basic block references.
196///
197/// Return true if an error occurred.
198bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,
199                                       StringRef Src, SMDiagnostic &Error);
200
201/// Parse the machine instructions.
202///
203/// This function runs the second parsing pass on the machine function's body.
204/// It skips the machine basic block definitions and parses only the machine
205/// instructions and basic block attributes like liveins and successors.
206///
207/// The second parsing pass assumes that the first parsing pass already ran
208/// on the given source string.
209///
210/// Return true if an error occurred.
211bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
212                              SMDiagnostic &Error);
213
214bool parseMBBReference(PerFunctionMIParsingState &PFS,
215                       MachineBasicBlock *&MBB, StringRef Src,
216                       SMDiagnostic &Error);
217
218bool parseRegisterReference(PerFunctionMIParsingState &PFS,
219                            unsigned &Reg, StringRef Src,
220                            SMDiagnostic &Error);
221
222bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
223                                 StringRef Src, SMDiagnostic &Error);
224
225bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
226                                   VRegInfo *&Info, StringRef Src,
227                                   SMDiagnostic &Error);
228
229bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
230                               StringRef Src, SMDiagnostic &Error);
231
232bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
233                 SMDiagnostic &Error);
234
235} // end namespace llvm
236
237#endif // LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
238