Target/AMDGPU/SIInstrInfo.cpp

488                                          ? MRI.getRegClass(Reg)
763   const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
829     RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
830   assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
2135     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2136     assert(MRI.getRegClass(FalseReg) == RC);
2149     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2150     assert(MRI.getRegClass(FalseReg) == RC);
2177   const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2383       if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2386       if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2453                      RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2469                     RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
3124     return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
3301       const TargetRegisterClass *RC = RI.getRegClass(RegClass);
3825       return MRI.getRegClass(Reg);
3830   return RI.getRegClass(RCID);
3841   const TargetRegisterClass *RC = RI.getRegClass(RCID);
3930                                       ? MRI.getRegClass(Reg)
3933   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
3966       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
4149     if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
4155     if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
4195     if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&
4201     if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
4222   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
4270   if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
4275   if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
4341   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4422   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4555           MRI.getRegClass(MI.getOperand(i).getReg());
4616         const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
4634     const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
4635     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
4647     if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
4661     if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4667     if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
4681     if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
4682                              RI.getRegClass(RsrcRC))) {
4711       const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5200                       RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
5202                       RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
5309     MRI.getRegClass(Src0.getReg()) :
5317   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5356   const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5371   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5372   const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
5436     MRI.getRegClass(Src0.getReg()) :
5441     MRI.getRegClass(Src1.getReg()) :
5455   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5498   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5540     MRI.getRegClass(Src.getReg()) :
5823     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
5830     const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
6279   return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);