Searched refs:TII (Results 276 - 300 of 388) sorted by relevance

<<111213141516

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1266 const TargetInstrInfo &TII,
1276 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1465 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
1594 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1595 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1598 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1619 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
1623 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1628 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1640 BuildMI(BB, DL, TII
1264 insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit, bool IsMicroMips) argument
1657 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
1850 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
1905 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
4552 const TargetInstrInfo *TII = local
4629 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp66 if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo())
67 if (getMachineOpcode() < TII->getNumOpcodes())
68 return TII->getName(getMachineOpcode());
150 else if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo())
151 return TII->getName(IID);
478 const TargetInstrInfo *TII, LLVMContext &Ctx) {
483 MMO.print(OS, MST, SSNs, Ctx, MFI, TII);
496 /*MFI=*/nullptr, /*TII=*/nullptr, Ctx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCSE.cpp66 const TargetInstrInfo *TII; member in class:__anon1749::MachineCSE
457 if (TII->isAsCheapAsAMove(*MI)) {
542 if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
551 (void)TII->commuteInstruction(*MI);
833 TII->duplicate(*CMBB, CMBB->getFirstTerminator(), *MI);
886 TII = MF.getSubtarget().getInstrInfo();
892 LookAheadLimit = TII->getMachineCSELookAheadLimit();
H A DTargetInstrInfo.cpp471 const TargetInstrInfo &TII) {
502 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
518 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
780 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local
782 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
839 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
843 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
1155 const auto &TII = MF->getSubtarget().getInstrInfo(); local
1166 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
469 foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, int FrameIndex, const TargetInstrInfo &TII) argument
H A DShrinkWrap.cpp199 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local
200 FrameSetupOpcode = TII.getCallFrameSetupOpcode();
201 FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
H A DRenameIndependentSubregs.cpp106 const TargetInstrInfo *TII; member in class:__anon1801::RenameIndependentSubregs
332 const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF);
387 TII = MF.getSubtarget().getInstrInfo();
H A DScoreboardHazardRecognizer.cpp179 if (DAG->TII->isZeroCost(MCID->Opcode))
H A DBranchFolding.h128 const TargetInstrInfo *TII; member in class:llvm::BranchFolder
H A DMachineRegisterInfo.cpp123 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local
137 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
472 const TargetInstrInfo &TII) {
487 TII.get(TargetOpcode::COPY), LiveIns[i].second)
470 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
H A DPostRASchedulerList.cpp81 const TargetInstrInfo *TII = nullptr; member in class:__anon1785::PostRAScheduler
286 TII = Fn.getSubtarget().getInstrInfo();
343 if (MI.isCall() || TII->isSchedulingBoundary(MI, &MBB, Fn)) {
685 TII->insertNoop(*BB, RegionEnd);
H A DVirtRegMap.cpp64 TII = mf.getSubtarget().getInstrInfo();
178 const TargetInstrInfo *TII; member in class:__anon1837::VirtRegRewriter
238 TII = MF->getSubtarget().getInstrInfo();
387 MI.setDesc(TII->get(TargetOpcode::KILL));
H A DLiveDebugValues.cpp118 const TargetInstrInfo *TII; member in class:__anon1733::LiveDebugValues
748 auto DestSrc = TII->isCopyInstr(*I);
799 /*AddNewLine*/ true, TII)); local
968 if (!MI.getSpillSize(TII) && !MI.getFoldedSpillSize(TII))
1023 if (MI.getRestoreSize(TII)) {
1117 auto DestSrc = TII->isCopyInstr(MI);
1636 TII = MF.getSubtarget().getInstrInfo();
H A DMachineInstrBundle.cpp132 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local
136 BuildMI(MF, getDebugLoc(FirstMI, LastMI), TII->get(TargetOpcode::BUNDLE));
H A DCalcSpillWeights.cpp88 const TargetInstrInfo &TII) {
132 if (!TII.isTriviallyReMaterializable(*MI, LIS.getAliasAnalysis()))
85 isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, VirtRegMap *VRM, const TargetInstrInfo &TII) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp99 const PPCInstrInfo *TII; member in struct:__anon2375::PPCVSXSwapRemoval
222 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
803 TII->get(PPC::XXPERMDI), DstReg)
917 TII->get(PPC::COPY), VSRCTmp1)
925 TII->get(PPC::COPY), DstReg)
951 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
978 dbgs() << format(" %14s ", TII->getName(MI->getOpcode()).str().c_str());
H A DPPCReduceCRLogicals.cpp155 const PPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); local
221 TII->get(NewBROpcode))
225 TII->get(PPC::B))
238 FirstTerminator->setDesc(TII->get(InvertedOpcode));
379 const PPCInstrInfo *TII = nullptr; member in class:__anon2368::PPCReduceCRLogicals
548 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
571 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LoadValueInjectionLoadHardening.cpp156 const TargetInstrInfo *TII; member in class:__anon112::X86LoadValueInjectionLoadHardeningPass
270 TII = STI->getInstrInfo();
333 TargetOperandInfo TOI{*TII};
334 DataFlowGraph DFG{MF, *TII, *TRI, MDT, MDF, TOI};
768 BuildMI(*MBB, InsertionPt, DebugLoc(), TII->get(X86::LFENCE));
874 const TargetInstrInfo *TII = STI->getInstrInfo(); local
883 BuildMI(MBB, InsertionPt, DebugLoc(), TII->get(X86::LFENCE));
H A DX86OptimizeLEAs.cpp307 const X86InstrInfo *TII = nullptr; member in class:__anon2515::X86OptimizeLEAPass
365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=
592 return BuildMI(*MBB, MBB->erase(&MI), DL, TII->get(TargetOpcode::DBG_VALUE),
691 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMCInstLower.cpp178 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); local
188 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
200 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
H A DAMDGPURegisterBankInfo.h46 const SIInstrInfo *TII; member in class:llvm::AMDGPURegisterBankInfo
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1443 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local
1528 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1529 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1536 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1541 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1547 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1551 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1554 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1558 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1582 const TargetInstrInfo &TII local
1622 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent() local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h36 const TargetInstrInfo *TII; member in class:llvm::RegScavenger
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1431 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); local
1466 BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1472 BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1512 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1514 BuildMI(BB, dl, TII.get(MSP430::JCC))
1523 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1526 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1530 BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1533 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1537 BuildMI(LoopBB, dl, TII
1566 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); local
[all...]
H A DMSP430InstrInfo.cpp313 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); local
314 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h314 StackOffset Offset, const TargetInstrInfo *TII,
324 const AArch64InstrInfo *TII);

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