1//===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15
16#include "llvm/ADT/SmallSet.h"
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/Register.h"
19#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
20
21#define GET_REGBANK_DECLARATIONS
22#include "AMDGPUGenRegisterBank.inc"
23#undef GET_REGBANK_DECLARATIONS
24
25namespace llvm {
26
27class LLT;
28class GCNSubtarget;
29class MachineIRBuilder;
30class SIInstrInfo;
31class SIRegisterInfo;
32class TargetRegisterInfo;
33
34/// This class provides the information for the target register banks.
35class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
36
37protected:
38
39#define GET_TARGET_REGBANK_CLASS
40#include "AMDGPUGenRegisterBank.inc"
41};
42class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
43public:
44  const GCNSubtarget &Subtarget;
45  const SIRegisterInfo *TRI;
46  const SIInstrInfo *TII;
47
48  bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
49
50  bool collectWaterfallOperands(
51    SmallSet<Register, 4> &SGPROperandRegs,
52    MachineInstr &MI,
53    MachineRegisterInfo &MRI,
54    ArrayRef<unsigned> OpIndices) const;
55
56  bool executeInWaterfallLoop(
57    MachineIRBuilder &B,
58    iterator_range<MachineBasicBlock::iterator> Range,
59    SmallSet<Register, 4> &SGPROperandRegs,
60    MachineRegisterInfo &MRI) const;
61
62  bool executeInWaterfallLoop(MachineIRBuilder &B,
63                              MachineInstr &MI,
64                              MachineRegisterInfo &MRI,
65                              ArrayRef<unsigned> OpIndices) const;
66  bool executeInWaterfallLoop(MachineInstr &MI,
67                              MachineRegisterInfo &MRI,
68                              ArrayRef<unsigned> OpIndices) const;
69
70  void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
71                                    unsigned OpIdx) const;
72  bool applyMappingWideLoad(MachineInstr &MI,
73                            const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
74                            MachineRegisterInfo &MRI) const;
75  bool
76  applyMappingImage(MachineInstr &MI,
77                    const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
78                    MachineRegisterInfo &MRI, int RSrcIdx) const;
79
80  void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const;
81
82  Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
83                          Register Reg) const;
84
85  std::pair<Register, unsigned>
86  splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
87
88  MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
89                                     MachineInstr &MI) const;
90
91  /// See RegisterBankInfo::applyMapping.
92  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
93
94  const RegisterBankInfo::InstructionMapping &
95  getInstrMappingForLoad(const MachineInstr &MI) const;
96
97  unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
98                        const TargetRegisterInfo &TRI,
99                        unsigned Default = AMDGPU::VGPRRegBankID) const;
100
101  // Return a value mapping for an operand that is required to be an SGPR.
102  const ValueMapping *getSGPROpMapping(Register Reg,
103                                       const MachineRegisterInfo &MRI,
104                                       const TargetRegisterInfo &TRI) const;
105
106  // Return a value mapping for an operand that is required to be a VGPR.
107  const ValueMapping *getVGPROpMapping(Register Reg,
108                                       const MachineRegisterInfo &MRI,
109                                       const TargetRegisterInfo &TRI) const;
110
111  // Return a value mapping for an operand that is required to be a AGPR.
112  const ValueMapping *getAGPROpMapping(Register Reg,
113                                       const MachineRegisterInfo &MRI,
114                                       const TargetRegisterInfo &TRI) const;
115
116  /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
117  /// Regs. This appropriately sets the regbank of the new registers.
118  void split64BitValueForMapping(MachineIRBuilder &B,
119                                 SmallVector<Register, 2> &Regs,
120                                 LLT HalfTy,
121                                 Register Reg) const;
122
123  template <unsigned NumOps>
124  struct OpRegBankEntry {
125    int8_t RegBanks[NumOps];
126    int16_t Cost;
127  };
128
129  template <unsigned NumOps>
130  InstructionMappings
131  addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
132                      const std::array<unsigned, NumOps> RegSrcOpIdx,
133                      ArrayRef<OpRegBankEntry<NumOps>> Table) const;
134
135  RegisterBankInfo::InstructionMappings
136  getInstrAlternativeMappingsIntrinsic(
137      const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
138
139  RegisterBankInfo::InstructionMappings
140  getInstrAlternativeMappingsIntrinsicWSideEffects(
141      const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
142
143  bool isSALUMapping(const MachineInstr &MI) const;
144
145  const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
146  const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
147  const InstructionMapping &getDefaultMappingAllVGPR(
148    const MachineInstr &MI) const;
149
150  const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI,
151                                            const MachineInstr &MI,
152                                            int RsrcIdx) const;
153
154public:
155  AMDGPURegisterBankInfo(const GCNSubtarget &STI);
156
157  unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
158                    unsigned Size) const override;
159
160  unsigned getBreakDownCost(const ValueMapping &ValMapping,
161                            const RegisterBank *CurBank = nullptr) const override;
162
163  const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
164                                             LLT) const override;
165
166  InstructionMappings
167  getInstrAlternativeMappings(const MachineInstr &MI) const override;
168
169  const InstructionMapping &
170  getInstrMapping(const MachineInstr &MI) const override;
171};
172} // End llvm namespace.
173#endif
174