/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 222 std::string Subtarget = SchedModel.getSubtargetInfo()->getCPU(); local 223 auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget); 291 std::string Subtarget = SchedModel.getSubtargetInfo()->getCPU(); local 292 if (InterlEarlyExit.find(Subtarget) != InterlEarlyExit.end()) 293 return InterlEarlyExit[Subtarget]; 300 InterlEarlyExit[Subtarget] = false; 305 InterlEarlyExit[Subtarget] = true;
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H A D | AArch64InstrInfo.cpp | 72 RI(STI.getTargetTriple()), Subtarget(STI) {} 686 if (!Subtarget.hasCustomCheapAsMoveHandling()) 693 if (Subtarget.hasZeroCycleZeroingFP()) { 700 if (Subtarget.hasZeroCycleZeroingGP()) { 709 if (Subtarget.hasExynosCheapAsMoveHandling()) { 1475 auto &Subtarget = MBB.getParent()->getSubtarget<AArch64Subtarget>(); local 1476 auto TRI = Subtarget.getRegisterInfo(); 1506 unsigned OpFlags = Subtarget.ClassifyGlobalReference(GV, TM); 1512 if (Subtarget.isTargetILP32()) { 1527 assert(!Subtarget 6238 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); local [all...] |
H A D | AArch64CallLowering.cpp | 451 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>(); local 452 if (!Subtarget.isTargetDarwin()) { 459 StackOffset = alignTo(Handler.StackUsed, Subtarget.isTargetILP32() ? 4 : 8); 485 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>(); local 486 if (Subtarget.hasCustomCallingConv()) 487 Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ShrinkWrap.cpp | 198 const TargetSubtargetInfo &Subtarget = MF.getSubtarget(); local 199 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 202 SP = Subtarget.getTargetLowering()->getStackPointerRegisterToSaveRestore();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 32 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 34 const SparcSubtarget *Subtarget = nullptr; member in class:__anon2398::SparcDAGToDAGISel 39 Subtarget = &MF.getSubtarget<SparcSubtarget>(); 69 unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 206 if (Subtarget.useHVXOps()) 329 if (Subtarget.useHVXOps()) 401 if (Subtarget.useHVXOps()) 427 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); 439 bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT()); 491 if (NeedsArgAlign && Subtarget.hasV60Ops()) { 612 Subtarget.isHVXVectorType(VT.getSimpleVT()); 625 return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V); 632 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); 726 auto &HFI = *Subtarget [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCCState.h | 27 const MipsSubtarget &Subtarget);
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H A D | MipsInstrInfo.h | 45 const MipsSubtarget &Subtarget; member in class:llvm::MipsInstrInfo
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H A D | MipsInstrInfo.cpp | 41 Subtarget(STI), UncondBrOpc(UncondBr) {} 443 if (Subtarget.inMicroMipsMode()) { 451 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) 465 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) && 474 if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) { 605 // Subtarget.getABI().GetZeroReg() when those atomic sequences and others 795 if (!Subtarget.useIndirectJumpsHazard())
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H A D | MicroMipsSizeReduction.cpp | 141 const MipsSubtarget *Subtarget; member in class:__anon2316::MicroMipsSizeReduce 777 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); 780 if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() || 781 Subtarget->hasMips32r6()) 784 MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
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H A D | MipsFastISel.cpp | 135 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can 138 const MipsSubtarget *Subtarget; member in class:__anon2323::final 258 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()), 259 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) { 262 UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat(); 1165 if (Subtarget->isFP64bit()) 1175 if (Subtarget->isFP64bit()) 1258 if (ArgSize < 8 && !Subtarget [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.h | 26 const R600Subtarget *Subtarget; member in class:llvm::final
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H A D | AMDGPURegisterBankInfo.h | 44 const GCNSubtarget &Subtarget; member in class:llvm::AMDGPURegisterBankInfo
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H A D | AMDGPUCallLowering.cpp | 440 const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>(); local 443 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo(); 455 const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F); 583 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); local 584 const SIRegisterInfo *TRI = Subtarget.getRegisterInfo(); 684 if (Subtarget.isAmdPalOS()) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelDAGToDAG.cpp | 30 : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {} 56 const AVRSubtarget *Subtarget; member in class:llvm::AVRDAGToDAGISel 60 Subtarget = &MF.getSubtarget<AVRSubtarget>(); 367 assert(Subtarget->hasLPM() && "cannot load from program memory on this mcu");
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEInstrInfo.cpp | 39 Subtarget(ST) {}
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.h | 52 const WebAssemblySubtarget *Subtarget; member in class:llvm::final
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZTargetMachine.cpp | 158 Subtarget(TT, CPU, FS, *this) {
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H A D | SystemZISelDAGToDAG.cpp | 135 const SystemZSubtarget *Subtarget; member in class:__anon2408::SystemZDAGToDAGISel 147 return Subtarget->getInstrInfo(); 357 Subtarget = &MF.getSubtarget<SystemZSubtarget>(); 999 Subtarget->hasLoadAndZeroRightmostByte()) 1024 if (Subtarget->hasMiscellaneousExtensions()) 1027 if (VT == MVT::i32 && Subtarget->hasHighWord() && 1094 if (Subtarget->hasMiscellaneousExtensions()) 1493 if (Subtarget->hasMiscellaneousExtensions3()) { 1549 (Subtarget->hasLoadStoreOnCond2() && 1592 if (VCI.isVectorConstantLegal(*Subtarget)) { [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 393 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { argument 394 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 740 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); local 741 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 743 OutMI.setOpcode(getRetOpcode(Subtarget)); 1189 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); 1195 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(), 1223 if (Subtarget->useIndirectThunkCalls()) 1288 bool Is64Bits = Subtarget->is64Bit(); 1328 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget [all...] |
H A D | X86SpeculativeLoadHardening.cpp | 161 const X86Subtarget *Subtarget = nullptr; member in class:__anon2518::X86SpeculativeLoadHardeningPass 408 Subtarget = &MF.getSubtarget<X86Subtarget>(); 410 TII = Subtarget->getInstrInfo(); 411 TRI = Subtarget->getRegisterInfo(); 1107 !Subtarget->isPositionIndependent()) { 1146 !Subtarget->isPositionIndependent()) { 2028 if (EFLAGSLive && !Subtarget->hasBMI2()) { 2040 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || 2042 assert(Subtarget->hasAVX2() && "AVX2-specific register classes!"); 2080 assert(Subtarget [all...] |
H A D | X86InterleavedAccess.cpp | 64 const X86Subtarget &Subtarget; member in class:__anon2964::X86InterleavedAccessGroup 114 : Inst(I), Shuffles(Shuffs), Indices(Ind), Factor(F), Subtarget(STarget), 140 if (!Subtarget.hasAVX() || (Factor != 4 && Factor != 3)) 817 X86InterleavedAccessGroup Grp(LI, Shuffles, Indices, Factor, Subtarget, 843 X86InterleavedAccessGroup Grp(SI, Shuffles, Indices, Factor, Subtarget,
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H A D | X86FlagsCopyLowering.cpp | 91 const X86Subtarget *Subtarget = nullptr; member in class:__anon2496::X86FlagsCopyLoweringPass 367 Subtarget = &MF.getSubtarget<X86Subtarget>(); 369 TII = Subtarget->getInstrInfo(); 370 TRI = Subtarget->getRegisterInfo(); 1027 if (TargetRegSize == 1 && !Subtarget->is64Bit()) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 73 const ARCSubtarget &Subtarget) 74 : TargetLowering(TM), Subtarget(Subtarget) { 79 computeRegisterProperties(Subtarget.getRegisterInfo()); 344 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 710 const ARCRegisterInfo &ARI = *Subtarget.getRegisterInfo(); 72 ARCTargetLowering(const TargetMachine &TM, const ARCSubtarget &Subtarget) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 103 Subtarget(STI), RI(STI.getTargetMachine()) {} 205 unsigned Directive = Subtarget.getCPUDirective(); 272 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive) 472 unsigned Directive = Subtarget.getCPUDirective(); 500 bool isPPC64 = Subtarget.isPPC64(); 714 bool isPPC64 = Subtarget.isPPC64(); 957 assert(Subtarget.hasDirectMove() && 958 "Subtarget doesn't support directmove, don't know how to copy."); 965 assert(Subtarget.hasDirectMove() && 966 "Subtarget does [all...] |