Searched refs:Shift (Results 76 - 100 of 112) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1650 unsigned RegOpc, Shift; local
1654 Shift = 0;
1659 Shift = MI.getOperand(MI.mayLoad() ? 2 : 1).getImm();
1684 MIB.addImm(Shift); // << Shift
H A DHexagonHardwareLoops.cpp972 unsigned Shift = Log2_32(IVBump); local
974 // Generate NormR = LSR DistR, Shift.
979 .addImm(Shift);
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1490 int Shift = DstBit - SrcBit; local
1491 uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
1492 : LaneBitmask::BitWidth + Shift;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp599 // Shift the range if the compare is fed by an add. This is the range
5178 // Shift down.
5649 // one element and LLVM disallows duplicate cases, Shift is guaranteed to be
5651 unsigned Shift = 64; local
5653 Shift = std::min(Shift, countTrailingZeros((uint64_t)V));
5654 assert(Shift < 64);
5655 if (Shift > 0)
5657 V = (int64_t)((uint64_t)V >> Shift);
5665 // C & (1 << Shift
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1960 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); local
1963 if (Shift && Mask) {
1964 uint32_t ShiftVal = Shift->getZExtValue();
1982 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1)); local
1985 if (Shift && Mask) {
1986 uint32_t ShiftVal = Shift->getZExtValue();
2315 // Shift to offset in m0
H A DAMDGPULegalizerInfo.cpp1857 const unsigned Shift = countTrailingZeros<unsigned>(Mask);
1861 if (Shift != 0) {
1862 auto ShiftAmt = B.buildConstant(S32, Shift);
1866 B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2635 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi. member in struct:InstructionTable
2639 { // ARM Opc S Shift Imm
2647 { // Thumb Opc S Shift Imm
2657 { // ARM Opc S Shift Imm
2665 { // Thumb Opc S Shift Imm
2695 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; local
2696 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2707 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2722 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp6014 bool CodeGenPrepare::optimizeShiftInst(BinaryOperator *Shift) { argument
6015 assert(Shift->isShift() && "Expected a shift");
6027 Type *Ty = Shift->getType();
6031 if (!match(Shift->getOperand(1),
6037 IRBuilder<> Builder(Shift);
6038 BinaryOperator::BinaryOps Opcode = Shift->getOpcode();
6039 Value *NewTVal = Builder.CreateBinOp(Opcode, Shift->getOperand(0), TVal);
6040 Value *NewFVal = Builder.CreateBinOp(Opcode, Shift->getOperand(0), FVal);
6042 Shift->replaceAllUsesWith(NewSel);
6043 Shift
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1461 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1464 Shift = ARM_AM::lsl;
1467 Shift = ARM_AM::lsr;
1470 Shift = ARM_AM::asr;
1473 Shift = ARM_AM::ror;
1477 if (Shift == ARM_AM::ror && imm == 0)
1478 Shift = ARM_AM::rrx;
1480 unsigned Op = Shift | (imm << 3);
1500 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1503 Shift
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp11847 unsigned Shift = (NumElts - 1) - (Mask[ZeroLo + Len - 1] % NumElts);
11849 DAG.getTargetConstant(Scale * Shift, DL, MVT::i8));
11853 unsigned Shift = Mask[ZeroLo] % NumElts;
11855 DAG.getTargetConstant(Scale * Shift, DL, MVT::i8));
11862 unsigned Shift = (NumElts - 1) - (Mask[ZeroLo + Len - 1] % NumElts);
11864 DAG.getTargetConstant(Scale * Shift, DL, MVT::i8));
11865 Shift += Mask[ZeroLo] % NumElts;
11867 DAG.getTargetConstant(Scale * Shift, DL, MVT::i8));
11906 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
11908 for (int j = 0; j < Shift;
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1167 unsigned Shift = SmallVT.getScalarSizeInBits(); local
1170 DAG.getConstant(Shift, DL, ShiftTy));
1222 // Shift it to the right position and "or" it in.
2976 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy); local
2977 SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
2978 SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
2979 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
2984 SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
2988 SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
2994 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
[all...]
H A DLegalizeDAG.cpp2654 APInt Shift(Sz, 1);
2655 Shift <<= J;
2656 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
3344 SDValue Shift = DAG.getConstant(
3347 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3392 SDValue Shift =
3395 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
H A DSelectionDAG.cpp2871 unsigned Shift = ShAmt->getZExtValue();
2872 Known.Zero <<= Shift;
2873 Known.One <<= Shift;
2875 Known.Zero.setLowBits(Shift);
2892 unsigned Shift = ShAmt->getZExtValue();
2893 Known.Zero.lshrInPlace(Shift);
2894 Known.One.lshrInPlace(Shift);
2896 Known.Zero.setHighBits(Shift);
2912 unsigned Shift = ShAmt->getZExtValue();
2914 Known.Zero.ashrInPlace(Shift);
[all...]
H A DSelectionDAGISel.cpp2294 unsigned Shift = 7; local
2298 Val |= (NextBits&127) << Shift;
2299 Shift += 7;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCAsmStreamer.cpp1013 uint64_t Shift = 64 - EmissionSize * 8; local
1014 assert(Shift < static_cast<uint64_t>(
1017 ValueToEmit &= ~0ULL >> Shift;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1843 unsigned Shift = (Imm & 0x100) ? 8 : 0; local
1844 if (ElementWidth == 8 && Shift)
1847 Inst.addOperand(MCOperand::createImm(Shift));
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/
H A DExpr.cpp1142 int Shift = 28; local
1143 while ((Char >> Shift) == 0)
1144 Shift -= 4;
1145 for (/**/; Shift >= 0; Shift -= 4)
1146 OS << Hex[(Char >> Shift) & 15];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DMemorySanitizer.cpp2382 Value *Shift = IRB.CreateBinOp(I.getOpcode(), S1, V2);
2383 setShadow(&I, IRB.CreateOr(Shift, S2Conv));
2719 Value *Shift = IRB.CreateCall(I.getFunctionType(), I.getCalledValue(),
2721 Shift = IRB.CreateBitCast(Shift, getShadowTy(&I));
2722 setShadow(&I, IRB.CreateOr(Shift, S2Conv));
/freebsd-11-stable/contrib/gcc/config/arm/
H A Dieee754-sf.S115 @ Shift and add second arg to first arg in r0.
508 @ Shift value right, round, etc.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp668 static bool canShiftBinOpWithConstantRHS(BinaryOperator &Shift, argument
674 return Shift.getOpcode() == Instruction::Shl;
708 "Shift over the type width should have been removed already");
H A DInstCombineCalls.cpp400 // Handle cases when Shift >= BitWidth.
406 // If ArithmeticShift - clamp Shift to (BitWidth - 1).
1967 "Shift amount expected to be modulo bitwidth");
2451 uint64_t Shift = C->getZExtValue(); local
2452 uint64_t Length = (Shift >> 8) & 0xff;
2453 Shift &= 0xff;
2456 if (Length == 0 || Shift >= BitWidth)
2460 uint64_t Result = InC->getZExtValue() >> Shift;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp6543 int Shift = MI.getOperand(3).getImm(); local
6544 assert((Shift == 0 || Shift == 12) && "Shift can be either 0 or 12");
6545 Offset = Offset << Shift;
6605 int Shift = MI.getOperand(2).getImm(); local
6606 return ParamLoadedValue(MachineOperand::CreateImm(Immediate << Shift),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1591 APInt Shift = SplatConst->getAPIntValue().zextOrTrunc(32); local
1593 DAG.getConstant(Shift, DL, MVT::i32));
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/StructuredData/DarwinLog/
H A DStructuredDataDarwinLog.cpp1005 args.Shift();
/freebsd-11-stable/contrib/llvm-project/lldb/source/Commands/
H A DCommandObjectMemory.cpp1396 command.Shift(); // shift off the address argument

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