Searched refs:STORE (Results 26 - 50 of 53) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp369 case ISD::STORE: return "store";
H A DLegalizeFloatTypes.cpp796 case ISD::STORE: Res = SoftenFloatOp_STORE(N, OpNo); break;
1672 case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
1977 case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
2054 // a STORE of the integer value.
2161 // STORE promotion handlers.
H A DLegalizeDAG.cpp503 switch (TLI.getOperationAction(ISD::STORE, VT)) {
527 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
642 // TRUNCSTORE:i16 i32 -> STORE i16
1059 case ISD::STORE:
1060 // FIXME: Model these properly. LOAD and STORE are complicated, and
1061 // STORE expects the unlegalized operand in some cases.
1279 case ISD::STORE:
H A DLegalizeVectorTypes.cpp595 case ISD::STORE:
1936 case ISD::STORE:
4193 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
H A DLegalizeVectorOps.cpp289 } else if (Op.getOpcode() == ISD::STORE) {
H A DDAGCombiner.cpp1604 case ISD::STORE: return visitSTORE(N);
6617 if (LegalOperations && !TLI.isOperationLegal(ISD::STORE, VT))
15239 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
15241 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
16334 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
16346 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
16355 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
16402 TLI.isOperationLegal(ISD::STORE, SVT)) &&
16434 // Try transforming several stores into STORE (BSWAP).
16596 case ISD::STORE
[all...]
H A DTargetLowering.cpp236 if (isOperationLegalOrCustom(ISD::STORE, NewVT) &&
240 isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
6845 if (!isOperationLegalOrCustom(ISD::STORE, intVT) &&
H A DLegalizeIntegerTypes.cpp1285 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
3782 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
H A DSelectionDAG.cpp569 case ISD::STORE: {
6949 AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
7016 AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
7045 AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
877 if (Opc != ISD::LOAD && Opc != ISD::STORE)
H A DPPCISelLowering.cpp233 setOperationAction(ISD::STORE, MVT::i1, Custom);
648 setOperationAction(ISD::STORE, VT, Promote);
649 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
726 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
834 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
876 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
877 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
997 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
1048 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
1093 setOperationAction(ISD::STORE , MV
[all...]
H A DPPCISelDAGToDAG.cpp213 // tryTLSXFormStore - Convert an ISD::STORE fed by a PPCISD::ADD_TLS into
1050 case ISD::STORE: {
4625 case ISD::STORE: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1455 setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1461 setOperationAction(ISD::STORE, MVT::i64, Custom);
1465 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1592 // Custom Lower Atomic LOAD/STORE
1704 setOperationAction(ISD::STORE, MVT::f128, Legal);
1707 setOperationAction(ISD::STORE, MVT::f128, Custom);
3037 case ISD::STORE: return LowerSTORE(Op, DAG);
/freebsd-11-stable/contrib/libarchive/libarchive/
H A Darchive_read_support_format_rar5.c3753 STORE = 0, FASTEST = 1, FAST = 2, NORMAL = 3, GOOD = 4, enumerator in enum:COMPRESSION_METHOD
3761 case STORE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1559 setOperationAction(ISD::STORE, VT, Custom);
2912 case ISD::STORE: return LowerStore(Op, DAG);
2954 if (N->getOpcode() != ISD::STORE)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp467 setOperationAction(ISD::STORE, MVT::i1, Custom);
487 setOperationAction(ISD::STORE, VT, Custom);
2191 case ISD::STORE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1615 case Store: return ISD::STORE;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1610 case ISD::STORE: {
H A DSystemZISelLowering.cpp337 setOperationAction(ISD::STORE, VT, Legal);
636 setTargetDAGCombine(ISD::STORE);
5784 // Combine STORE (BSWAP) into STRVH/STRV/STRVG/VSTBR
5803 // Combine STORE (element-swap) into VSTER
6386 case ISD::STORE: return combineSTORE(N, DCI);
6936 // happen when the condition is false rather than true. If a STORE ON
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp162 setOperationAction(ISD::STORE, VT, Promote);
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
242 setOperationAction(ISD::STORE, VT, Legal);
418 setOperationAction(ISD::STORE, VT, Custom);
942 setTargetDAGCombine(ISD::STORE);
9365 case ISD::STORE:
13078 const bool isStore = N->getOpcode() == ISD::STORE;
13158 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
13257 // If this is a non-standard-aligned STORE, the penultimate operand is the
13259 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
[all...]
H A DARMISelDAGToDAG.cpp1384 case ISD::STORE:
3113 case ISD::STORE: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp548 setOperationAction(ISD::STORE, MVT::i128, Custom);
649 setTargetDAGCombine(ISD::STORE);
874 setOperationPromotedToType(ISD::STORE, VT, PromoteTo);
3266 case ISD::STORE:
12591 case ISD::STORE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp374 setOperationAction(ISD::STORE, MVT::i64, Custom);
1242 case ISD::STORE: return lowerSTORE(Op, DAG);
3344 // emit ISD::STORE whichs stores the
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp356 if (User->getOpcode() == ISD::STORE &&
5266 case ISD::STORE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp741 if (Opc == ISD::LOAD || Opc == ISD::STORE || isa<AtomicSDNode>(N) ||
756 // calculation into the LOAD and STORE instructions.

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