Searched refs:Regs (Results 26 - 50 of 62) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp388 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); local
390 for (unsigned i = 0; Regs[i]; ++i)
391 if (RISCV::FPR32RegClass.contains(Regs[i]) ||
392 RISCV::FPR64RegClass.contains(Regs[i]))
393 SavedRegs.set(Regs[i]);
H A DRISCVISelLowering.h224 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { argument
1123 return createTuple(Regs, RegClassIDs, SubRegs);
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { argument
1132 return createTuple(Regs, RegClassIDs, SubRegs);
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, argument
1140 if (Regs.size() == 1)
1141 return Regs[0];
1143 assert(Regs.size() >= 2 && Regs.size() <= 4);
1145 SDLoc DL(Regs[
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H A DAArch64CallLowering.cpp235 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
241 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
247 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0],
352 if (CurVReg != CurArgInfo.Regs[0]) {
353 CurArgInfo.Regs[0] = CurVReg;
631 if (OutInfo.Regs.size() > 1) {
640 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp999 RegisterSet Regs[2];
1002 Regs[S].insert(VR);
1004 while (!Regs[S].empty()) {
1007 Regs[OtherS].clear();
1008 for (unsigned R = Regs[S].find_first(); R; R = Regs[S].find_next(R)) {
1009 Regs[S].remove(R);
1032 getInstrUses(DefI, Regs[OtherS]);
1481 SmallVector<unsigned,2> Regs;
1490 Regs
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H A DHexagonFrameLowering.cpp1451 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { argument
1453 for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
2486 BitVector Regs(Hexagon::NUM_TARGET_REGS);
2491 Regs[R] = true;
2493 int F = Regs.find_first();
2497 int N = Regs.find_next(F);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp1058 SmallPtrSetImpl<const SCEV *> &Regs,
1068 SmallPtrSetImpl<const SCEV *> &Regs);
1070 SmallPtrSetImpl<const SCEV *> &Regs,
1181 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon2715::LSRUse
1238 SmallPtrSetImpl<const SCEV *> &Regs) {
1287 if (!Regs.count(AR->getOperand(1))) {
1288 RateRegister(F, AR->getOperand(1), Regs);
1310 SmallPtrSetImpl<const SCEV *> &Regs,
1316 if (Regs.insert(Reg).second) {
1317 RateRegister(F, Reg, Regs);
1237 RateRegister(const Formula &F, const SCEV *Reg, SmallPtrSetImpl<const SCEV *> &Regs) argument
1309 RatePrimaryRegister(const Formula &F, const SCEV *Reg, SmallPtrSetImpl<const SCEV *> &Regs, SmallPtrSetImpl<const SCEV *> *LoserRegs) argument
1323 RateFormula(const Formula &F, SmallPtrSetImpl<const SCEV *> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const LSRUse &LU, SmallPtrSetImpl<const SCEV *> *LoserRegs) argument
4312 SmallPtrSet<const SCEV *, 16> Regs; local
4600 SmallPtrSet<const SCEV *, 16> Regs; local
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h566 auto Regs = getOrCreateVRegs(Val); local
567 if (Regs.empty())
569 assert(Regs.size() == 1 &&
571 return Regs[0];
H A DLegalizationArtifactCombiner.h364 SmallVector<Register, 2> Regs; local
367 Regs.push_back(MergeI->getOperand(Idx).getReg());
370 Builder.buildMerge(DefReg, Regs);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.h117 /// Regs. This appropriately sets the regbank of the new registers.
119 SmallVector<Register, 2> &Regs,
H A DSIMachineFunctionInfo.cpp344 auto Regs = RC.getRegisters(); local
367 SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
370 NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
375 if (NextSpillReg == Regs.end()) { // Registers exhausted
H A DSIMachineScheduler.h395 void addLiveRegs(std::set<unsigned> &Regs);
396 void decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs);
H A DSILoadStoreOptimizer.cpp520 const unsigned Regs = getRegs(I->getOpcode(), TII); local
522 if (Regs & ADDR) {
526 if (Regs & SBASE) {
530 if (Regs & SRSRC) {
534 if (Regs & SOFFSET) {
538 if (Regs & VADDR) {
542 if (Regs & SSAMP) {
1236 const unsigned Regs = getRegs(Opcode, *TII); local
1238 if (Regs & VADDR)
1298 const unsigned Regs local
1377 const unsigned Regs = getRegs(Opcode, *TII); local
1539 const unsigned Regs = getRegs(Opcode, *TII); local
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H A DSIMachineScheduler.cpp367 // We want LiveOutRegs to contain only Regs whose content will be read after
1682 void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) { argument
1683 for (unsigned Reg : Regs) {
1693 std::set<unsigned> &Regs) {
1694 for (unsigned Reg : Regs) {
1692 decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp199 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, argument
228 Regs.push_back(MCPhysReg(Locs[I].getLocReg()));
H A DLiveDebugValues.cpp508 const DefinedRegsSet &Regs) const;
1440 static void collectRegDefs(const MachineInstr &MI, DefinedRegsSet &Regs, argument
1445 Regs.insert(*AI);
H A DRegisterPressure.cpp229 Regs.setUniverse(NumRegUnits + NumVirtRegs);
234 Regs.clear();
705 void RegPressureTracker::addLiveRegs(ArrayRef<RegisterMaskPair> Regs) {
706 for (const RegisterMaskPair &P : Regs) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp164 auto *Regs = VMap.getVRegs(Val); local
170 Regs->push_back(0);
171 return *Regs;
870 ArrayRef<Register> Regs = getOrCreateVRegs(LI);
878 assert(Regs.size() == 1 && "swifterror should be single pointer");
881 MIRBuilder.buildCopy(Regs[0], VReg);
886 Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr;
887 for (unsigned i = 0; i < Regs.size(); ++i) {
896 Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
899 MIRBuilder.buildLoad(Regs[
1032 auto &Regs = *VMap.getVRegs(U); local
1879 auto &Regs = *VMap.getVRegs(U); local
1903 auto &Regs = *VMap.getVRegs(U); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp427 unsigned RegisterFile::isAvailable(ArrayRef<MCPhysReg> Regs) const {
431 for (const MCPhysReg RegID : Regs) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp76 const MCPhysReg (&Regs)[N]) {
78 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
75 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg (&Regs)[N]) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp69 assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet");
78 if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
82 if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
716 ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp255 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
256 if (*Regs == ARM::CPSR)
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp355 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); local
356 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
357 if (I == Regs.end())
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp701 SDValue Regs[2]; local
702 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) &&
703 Regs[0].getNode() && Regs[1].getNode()) {
705 Base = Regs[I];
706 Index = Regs[1 - I];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp776 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
796 Regs.push_back(Reg + i);
829 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
831 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
840 if (!Register::isVirtualRegister(Regs[Part + i]) ||
845 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
898 unsigned NumRegs = Regs.size();
921 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
923 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
952 unsigned Flag = InlineAsm::getFlagWord(Code, Regs
5521 getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, const SDValue &N) argument
7950 SmallVector<unsigned, 4> Regs; local
8319 SmallVector<unsigned, 4> Regs; local
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