Searched refs:getReg (Results 26 - 50 of 244) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.cpp141 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
143 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
146 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
156 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
159 MI->getOperand(ValOpIdx).getReg());
161 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
340 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
341 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
346 MRI.setRegClass(MO.getReg(), newRegClass);
H A DR600EmitClauseMarkers.cpp64 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
126 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
157 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
186 TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
209 if (UseI->findRegisterUseOperandIdx(MOI->getReg()))
212 if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1)
H A DSIInstrInfo.cpp197 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
215 unsigned Reg = MI->getOperand(1).getReg();
316 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
319 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
323 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
325 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
326 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
327 if (SGPRUsed != MO.getReg()) {
329 SGPRUsed = MO.getReg();
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/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp154 unsigned Reg = II->getOperand(i).getReg();
239 cmpReg1 = MI->getOperand(1).getReg();
242 cmpOp2 = MI->getOperand(2).getReg();
427 predReg = MI->getOperand(0).getReg();
475 MI->getOperand(0).getReg() == predReg) {
494 cmpReg1 = MI->getOperand(1).getReg();
499 cmpOp2 = MI->getOperand(2).getReg();
518 (MI->getOperand(0).getReg() == cmpReg1 ||
520 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
522 unsigned feederReg = MI->getOperand(0).getReg();
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H A DHexagonVarargsCallingConvention.h57 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
69 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
113 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
125 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
/freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp70 O << MSP430InstPrinter::getRegisterName(MO.getReg());
119 if (Disp.isImm() && !Base.getReg())
124 if (Base.getReg()) {
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp422 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
444 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
455 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
484 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
496 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
508 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
519 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
530 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
543 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
544 Base = getReg(Decode
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/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/InstPrinter/
H A DSparcInstPrinter.cpp51 switch (MI->getOperand(0).getReg()) {
70 printRegName(O, MO.getReg());
96 if (MO.isReg() && MO.getReg() == SP::G0)
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp96 SrcReg = MI.getOperand(1).getReg();
97 DstReg = MI.getOperand(0).getReg();
120 return MI->getOperand(0).getReg();
144 return MI->getOperand(0).getReg();
174 unsigned Reg0 = MI->getOperand(0).getReg();
175 unsigned Reg1 = MI->getOperand(1).getReg();
176 unsigned Reg2 = MI->getOperand(2).getReg();
196 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
407 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg()
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/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp197 unsigned MOReg = MO.getReg();
201 UseRegs.insert(MO.getReg());
210 DefReg = MO.getReg();
270 unsigned MOReg = MO.getReg();
345 DstReg = MI.getOperand(0).getReg();
346 SrcReg = MI.getOperand(1).getReg();
348 DstReg = MI.getOperand(0).getReg();
349 SrcReg = MI.getOperand(2).getReg();
438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
442 DstReg = MI.getOperand(ti).getReg();
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H A DAntiDepBreaker.h64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
H A DDeadMachineInstructionElim.cpp69 unsigned Reg = MO.getReg();
127 unsigned Reg = MO.getReg();
155 unsigned Reg = MO.getReg();
174 unsigned Reg = MO.getReg();
H A DMachineSSAUpdater.cpp94 unsigned SrcReg = I->getOperand(i).getReg();
102 return I->getOperand(0).getReg();
152 return NewDef->getOperand(0).getReg();
204 return InsertedPHI->getOperand(0).getReg();
272 unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
300 return NewDef->getOperand(0).getReg();
311 return PHI->getOperand(0).getReg();
347 return PHI->getOperand(0).getReg();
H A DMachineCopyPropagation.cpp115 unsigned SrcSrc = CopyMI->getOperand(1).getReg();
119 unsigned SrcDef = CopyMI->getOperand(0).getReg();
151 unsigned Def = MI->getOperand(0).getReg();
152 unsigned Src = MI->getOperand(1).getReg();
241 unsigned Reg = MO.getReg();
273 unsigned Reg = (*DI)->getOperand(0).getReg();
311 if (!MRI->isReserved((*DI)->getOperand(0).getReg())) {
H A DMachineLICM.cpp433 unsigned Reg = MO.getReg();
540 unsigned Reg = MO.getReg();
567 if (!MO.isReg() || MO.isDef() || !MO.getReg())
569 unsigned Reg = MO.getReg();
597 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
598 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
773 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
817 unsigned Reg = MO.getReg();
849 unsigned Reg = MO.getReg();
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H A DTargetInstrInfo.cpp136 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
137 unsigned Reg1 = MI->getOperand(Idx1).getReg();
138 unsigned Reg2 = MI->getOperand(Idx2).getReg();
229 MO.setReg(Pred[j].getReg());
317 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
350 unsigned FoldReg = FoldOp.getReg();
351 unsigned LiveReg = LiveOp.getReg();
359 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
360 return RC->contains(LiveOp.getReg()) ? RC : 0;
431 storeRegToStackSlot(*MBB, Pos, MO.getReg(), M
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/freebsd-10.2-release/contrib/llvm/include/llvm/MC/MCParser/
H A DMCParsedAsmOperand.h49 virtual unsigned getReg() const = 0;
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/InstPrinter/
H A DX86IntelInstPrinter.cpp143 printRegName(O, Op.getReg());
161 if (SegReg.getReg()) {
169 if (BaseReg.getReg()) {
174 if (IndexReg.getReg()) {
188 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp131 if (MI->getOperand(1).getReg() != MI->getOperand(2).getReg()) {
166 if (opnd.isReg() && opnd.getReg() == p.getReg()){
227 if (p.isReg() && p.getReg() != X86::ESP) {
231 if (q.isReg() && q.getReg() != X86::ESP) {
H A DX86MCInstLower.cpp244 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
248 unsigned Reg = Inst.getOperand(0).getReg();
263 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
309 unsigned Reg = Inst.getOperand(RegOp).getReg();
325 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
326 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
327 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
352 MCOp = MCOperand::CreateReg(MO.getReg());
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H A DX86AsmPrinter.cpp243 unsigned Reg = MO.getReg();
277 bool HasBaseReg = BaseReg.getReg() != 0;
279 BaseReg.getReg() == X86::RIP)
283 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
299 assert(IndexReg.getReg() != X86::ESP &&
306 if (IndexReg.getReg()) {
321 if (Segment.getReg()) {
338 if (SegReg.getReg()) {
346 if (BaseReg.getReg()) {
351 if (IndexReg.getReg()) {
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp263 unsigned Reg = MO.getReg();
273 unsigned Reg = MO.getReg();
346 unsigned Reg = MO.getReg();
386 if (MI->getOperand(1).getReg() == ARM::SP) {
420 unsigned BaseReg = MI->getOperand(0).getReg();
428 if (MI->getOperand(i).getReg() == BaseReg) {
442 unsigned BaseReg = MI->getOperand(1).getReg();
456 unsigned BaseReg = MI->getOperand(1).getReg();
476 OffsetReg = MI->getOperand(2).getReg();
535 if (MI->getOperand(1).getReg() !
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/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp535 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
552 TII->get(Mips::PHI), MI->getOperand(0).getReg())
553 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
554 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
598 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
599 .addReg(MI->getOperand(4).getReg());
616 TII->get(Mips::PHI), MI->getOperand(0).getReg())
617 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
618 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
663 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp567 unsigned getReg() const { function in class:__anon2479::ARMOperand
1572 Inst.addOperand(MCOperand::CreateReg(getReg()));
1577 Inst.addOperand(MCOperand::CreateReg(getReg()));
2511 OS << "<ccout " << getReg() << ">";
2566 OS << "<register " << getReg() << ">";
2726 int SrcReg = PrevOp->getReg();
4148 ((ARMOperand*)Operands[4])->getReg() ==
4149 ((ARMOperand*)Operands[3])->getReg())
4865 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4873 static_cast<ARMOperand*>(Operands[1])->getReg()
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/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
106 unsigned Reg = MI->getOperand(0).getReg();
120 unsigned DestReg = MI->getOperand(0).getReg();
121 unsigned SrcReg = MI->getOperand(1).getReg();
140 unsigned Reg = MI->getOperand(0).getReg();
152 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
199 MI->getOperand(3).getReg() == 0) {
201 return MI->getOperand(0).getReg();
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