Lines Matching refs:getReg
63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
106 unsigned Reg = MI->getOperand(0).getReg();
120 unsigned DestReg = MI->getOperand(0).getReg();
121 unsigned SrcReg = MI->getOperand(1).getReg();
140 unsigned Reg = MI->getOperand(0).getReg();
152 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
199 MI->getOperand(3).getReg() == 0) {
201 return MI->getOperand(0).getReg();
407 SrcReg = MI->getOperand(0).getReg();
428 !MI->getOperand(2).getReg() &&
434 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
449 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
627 MI->getOperand(3).getReg() == 0);
667 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
691 unsigned DestReg = Dest.getReg();
692 unsigned SrcReg = Src.getReg();
710 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
738 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
758 !MI->getOperand(3).getReg()) {
773 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
801 unsigned Dest = MI->getOperand(0).getReg();
1011 bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
1012 bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());