ARM/AsmParser/ARMAsmParser.cpp

567   unsigned getReg() const {
1572     Inst.addOperand(MCOperand::CreateReg(getReg()));
1577     Inst.addOperand(MCOperand::CreateReg(getReg()));
2511     OS << "<ccout " << getReg() << ">";
2566     OS << "<register " << getReg() << ">";
2726   int SrcReg = PrevOp->getReg();
4148       ((ARMOperand*)Operands[4])->getReg() ==
4149         ((ARMOperand*)Operands[3])->getReg())
4865       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4873       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4884       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4885       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4904         isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4905         isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4910     if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4923       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4931       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4932        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4933        !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4935        (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4936         static_cast<ARMOperand*>(Operands[5])->getReg() &&
4937         static_cast<ARMOperand*>(Operands[3])->getReg() !=
4938         static_cast<ARMOperand*>(Operands[4])->getReg())))
4944       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4950       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4951        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4965       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4966       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4987              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4989              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5234     if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5235         MRC.contains(Op2->getReg())) {
5236       unsigned Reg1 = Op1->getReg();
5237       unsigned Reg2 = Op2->getReg();
5265       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5267       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5290     unsigned OpReg = Inst.getOperand(i).getReg();
5304     unsigned OpReg = Inst.getOperand(i).getReg();
5366     const unsigned RtReg = Inst.getOperand(0).getReg();
5380     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5386       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5401     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5402     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5410     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5411     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5420     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5421     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5445     unsigned Rn = Inst.getOperand(0).getReg();
5479     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5510         (((ARMOperand*)Operands[3])->getReg() !=
5511          ((ARMOperand*)Operands[5])->getReg()) &&
5512         (((ARMOperand*)Operands[3])->getReg() !=
5513          ((ARMOperand*)Operands[4])->getReg())) {
5540     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5558         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5853     if (Inst.getOperand(1).getReg() != ARM::PC ||
5854         Inst.getOperand(5).getReg() != 0)
5924     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5948     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5950     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5974     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5976     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5978     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6022     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6046     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6048     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6072     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6074     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6076     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6116     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6138     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6140     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6162     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6164     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6166     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6208     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6215     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6235     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6237     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6244     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6246     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6266     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6268     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6270     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6277     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6279     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6281     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6322     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6329     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6349     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6351     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6358     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6360     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6380     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6382     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6384     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6391     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6393     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6395     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6434     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6439     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6459     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6461     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6466     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6468     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6488     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6490     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6492     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6497     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6499     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6501     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6521     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6523     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6567     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6569     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6592     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6594     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6614     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6616     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6638     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6640     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6663     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6665     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6667     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6687     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6691     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6713     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6715     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6717     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6740     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6742     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6744     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6764     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6766     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6768     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6790     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6792     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6794     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6819     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6821     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6843     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6845     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6867     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6869     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6890     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6892     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6894     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6916     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6918     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6920     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6942     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6944     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6946     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6958     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6959         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6960         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6992     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6993         isARMLowRegister(Inst.getOperand(1).getReg()) &&
6994         isARMLowRegister(Inst.getOperand(2).getReg()) &&
6995         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7028     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7029         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7240     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7241         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7243         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7244         (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7265     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7266         Inst.getOperand(5).getReg() != 0 ||
7283     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7323     unsigned Rn = Inst.getOperand(0).getReg();
7338                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7347     unsigned Rn = Inst.getOperand(0).getReg();
7385     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7388          Inst.getOperand(4).getReg() == ARM::CPSR) ||
7389         (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7408     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7409         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7411         Inst.getOperand(4).getReg() == ARM::CPSR &&
7416       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7432     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7433         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7544     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7545          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7546         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7547         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7548          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7582     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7583          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7584         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7585          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7586         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7587          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7602       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7637     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7641     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7644     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7651            isARMLowRegister(Inst.getOperand(1).getReg()) &&
7652            isARMLowRegister(Inst.getOperand(2).getReg()))
7656            isARMLowRegister(Inst.getOperand(0).getReg()) &&
7657            isARMLowRegister(Inst.getOperand(1).getReg()))