lib/CodeGen/TwoAddressInstructionPass.cpp

197     unsigned MOReg = MO.getReg();
201       UseRegs.insert(MO.getReg());
210     DefReg = MO.getReg();
270       unsigned MOReg = MO.getReg();
345     DstReg = MI.getOperand(0).getReg();
346     SrcReg = MI.getOperand(1).getReg();
348     DstReg = MI.getOperand(0).getReg();
349     SrcReg = MI.getOperand(2).getReg();
438     if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
442       DstReg = MI.getOperand(ti).getReg();
594     unsigned RegA = MI->getOperand(0).getReg();
804     unsigned MOReg = MO.getReg();
822   while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
823     Defs.insert(End->getOperand(0).getReg());
847       unsigned MOReg = MO.getReg();
990     unsigned MOReg = MO.getReg();
1029       unsigned MOReg = MO.getReg();
1102   unsigned regA = MI.getOperand(DstIdx).getReg();
1103   unsigned regB = MI.getOperand(SrcIdx).getReg();
1126       regC = MI.getOperand(regCIdx).getReg();
1236                   TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1239                     if (NewMIs[0]->killsRegister(MO.getReg()))
1240                       LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1242                       assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1244                       LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1247                 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1248                   if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1249                     LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1251                     assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1253                     LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1266                 OrigRegs.push_back(MOI->getReg());
1311     unsigned SrcReg = SrcMO.getReg();
1312     unsigned DstReg = DstMO.getReg();
1357     unsigned RegA = DstMO.getReg();
1361     RegB = MI->getOperand(SrcIdx).getReg();
1382              MI->getOperand(i).getReg() != RegA);
1410     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1434         if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1470       if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1547           unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1548           unsigned DstReg = mi->getOperand(DstIdx).getReg();
1608   unsigned DstReg = MI->getOperand(0).getReg();
1618     OrigRegs.push_back(MI->getOperand(0).getReg());
1620       OrigRegs.push_back(MI->getOperand(i).getReg());
1626     unsigned SrcReg = UseMO.getReg();
1637         if (MI->getOperand(j).getReg() == SrcReg) {