Lines Matching refs:getReg
197 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
215 unsigned Reg = MI->getOperand(1).getReg();
316 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
319 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
323 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
325 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
326 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
327 if (SGPRUsed != MO.getReg()) {
329 SGPRUsed = MO.getReg();
399 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
453 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
459 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
467 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
488 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
491 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
493 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
494 SGPRReg = MO.getReg();
516 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
519 MRI.getRegClass(MI->getOperand(i).getReg());
543 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
575 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
617 unsigned DstReg = Inst->getOperand(0).getReg();