Searched refs:ARM (Results 26 - 50 of 70) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMJITInfo.cpp1 //===-- ARMJITInfo.cpp - Implement the JIT interfaces for the ARM target --===//
10 // This file implements the JIT interfaces for the ARM target.
16 #include "ARM.h"
105 #else // Not an ARM host
107 llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!");
239 ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
243 case ARM::reloc_arm_pic_jt:
246 case ARM::reloc_arm_jt_base:
249 case ARM
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H A DThumb1RegisterInfo.cpp16 #include "ARM.h"
50 if (ARM::tGPRRegClass.hasSubClassEq(RC))
51 return &ARM::tGPRRegClass;
58 return &ARM::tGPRRegClass;
78 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
111 if (DestReg == ARM::SP) {
112 assert(BaseReg == ARM::SP && "Unexpected!");
113 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
117 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM
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H A DA15SDOptimizer.cpp12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
28 #include "ARM.h"
57 return "ARM A15 S->D optimizer";
152 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
153 &ARM::DPRRegClass);
154 if (DReg != ARM::NoRegister) return ARM::ssub_1;
155 return ARM::ssub_0;
165 if (!MI) return ARM::ssub_0;
169 if (!MO) return ARM
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H A DARMBaseInstrInfo.h1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
17 #include "ARM.h"
336 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
346 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
351 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM
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H A DARMFastISel.cpp1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
16 #include "ARM.h"
248 if (MO.getReg() == ARM::CPSR)
279 // Are we NEON in ARM mode and have a predicate operand? If so, I know
285 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
540 TII.get(ARM::VMOVSR), MoveReg)
550 TII.get(ARM::VMOVRS), MoveReg)
569 Opc = ARM::FCONSTD;
572 Opc = ARM
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H A DThumb2ITBlockPass.cpp11 #include "ARM.h"
67 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
87 if (Reg == ARM::CPSR)
96 case ARM::MOVr:
97 case ARM::MOVr_TC:
98 case ARM::tMOVr:
99 case ARM::t2MOVr:
143 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
182 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM
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H A DARMCodeEmitter.cpp1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
10 // This file contains the pass that transforms the ARM machine instructions into
16 #include "ARM.h"
82 return "ARM Machine Code Emitter";
256 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
298 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
368 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
430 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM
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H A DARMConstantIslandPass.cpp1 //===-- ARMConstantIslandPass.cpp - ARM constant islands ------------------===//
12 // limited pc-relative displacements that ARM has.
17 #include "ARM.h"
73 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
272 return "ARM constant island placement and branch shortening pass";
416 // ARM and Thumb2 functions need to be 4-byte aligned.
545 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
602 assert(CPEMI && CPEMI->getOpcode() == ARM::CONSTPOOL_ENTRY);
625 if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
676 case ARM
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H A DARMISelLowering.cpp1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
17 #include "ARM.h"
71 cl::desc("Enable / disable ARM interworking (for debugging only)"),
91 ARM::R0, ARM::R1, ARM::R2, ARM::R3
154 addRegisterClass(VT, &ARM::DPRRegClass);
159 addRegisterClass(VT, &ARM
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H A DARMAsmPrinter.h1 //===-- ARMAsmPrinter.h - ARM implementation of AsmPrinter ------*- C++ -*-===//
13 #include "ARM.h"
22 namespace ARM { namespace in namespace:llvm
53 return "ARM Assembly / Object Emitter";
105 // ARM/Darwin adds ISA to the DWARF info for each function.
109 ARM::DW_ISA_ARM_thumb : ARM::DW_ISA_ARM_arm;
H A DThumb2RegisterInfo.cpp16 #include "ARM.h"
48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
H A DARMHazardRecognizer.cpp1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
36 assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
103 llvm_unreachable("reverse ARM hazard checking unsupported");
H A DARMBaseRegisterInfo.h1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
17 #include "ARM.h"
39 using namespace ARM;
54 using namespace ARM;
65 using namespace ARM;
87 /// FramePtr - ARM physical register used as frame ptr.
90 /// BasePtr - ARM physical register used as a base ptr in complex stack
H A DMLxExpansionPass.cpp16 #include "ARM.h"
46 return "ARM MLA / MLS expansion pass";
191 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
200 case ARM::VMULS:
201 case ARM::VMULfd:
202 case ARM::VMULfq:
203 case ARM::VMULD:
204 case ARM::VMULslfd:
205 case ARM
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/freebsd-10.2-release/lib/clang/liblldbPluginInstructionARM/
H A DMakefile7 SRCDIR= tools/lldb/source/Plugins/Instruction/ARM
/freebsd-10.2-release/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGBuiltin.cpp1880 return CGF.EmitARMBuiltinExpr(ARM::BI__builtin_neon_vget_lane_i8, E);
1893 return CGF.EmitARMBuiltinExpr(ARM::BI__builtin_neon_vset_lane_i8, E);
2911 // Handle ld1/st1 lane in this function a little different from ARM.
2933 // Handle ld1/st1 dup lane in this function a little different from ARM.
2975 // AArch64 builtins mapping to legacy ARM v7 builtins.
2979 return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vuzp_v, E);
2981 return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vuzpq_v, E);
2983 return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vzip_v, E);
2985 return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vzipq_v, E);
2987 return EmitARMBuiltinExpr(ARM
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMFixupKinds.h1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
16 namespace ARM { namespace in namespace:llvm
62 // The following fixups handle the ARM BL instructions. These can be
63 // conditionalised; however, the ARM ELF ABI requires a different relocation
71 // fixup_arm_uncondbl - Fixup for unconditional ARM BL instructions.
74 // fixup_arm_condbl - Fixup for ARM BL instructions with nontrivial
78 // fixup_arm_blx - Fixup for ARM BLX instructions.
H A DARMMCAsmInfo.cpp1 //===-- ARMMCAsmInfo.cpp - ARM asm properties -----------------------------===//
21 cl::desc("Generate ARM EHABI tables"),
57 ExceptionsType = ExceptionHandling::ARM;
H A DARMMCCodeEmitter.cpp1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
235 return MI.getOperand(Op).getReg() == ARM::CPSR;
428 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
429 case ARM
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H A DARMMCTargetDesc.cpp1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
10 // This file provides ARM specific target descriptions.
35 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
67 if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
91 // FIXME: Enhance Triple helper class to extract ARM version.
211 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
250 llvm_unreachable("ARM does not support Windows COFF format");
285 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
292 if (Inst.getOpcode() == ARM
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H A DARMELFStreamer.cpp1 //===- lib/MC/ARMELFStreamer.cpp - ELF Object Output for ARM --------------===//
10 // This file assembles .s files and emits ARM ELF .o object files. Different
58 #define ARM_FPU_NAME(NAME, ID) case ARM::ID: return NAME;
260 : ARMTargetStreamer(), CurrentVendor("aeabi"), FPU(ARM::INVALID_FPU),
267 /// ARM ELF ABI: infocenter.arm.com/help/topic/com.arm.../IHI0044D_aaelf.pdf.
270 /// region of ARM code, Thumb code or data in a section. In practice, this
293 // ARM exception handling directives
327 /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
335 /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
353 return; // Change to ARM mod
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/freebsd-10.2-release/lib/clang/libllvmarmdesc/
H A DMakefile7 SRCDIR= lib/Target/ARM/MCTargetDesc
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
10 // This class prints an ARM MCInst to a .s file.
82 case ARM::HINT:
83 case ARM::tHINT:
84 case ARM::t2HINT:
92 if ((getAvailableFeatures() & ARM::HasV8Ops)) {
103 if (Opcode == ARM::t2HINT)
109 case ARM::MOVsr: {
132 case ARM::MOVsi: {
161 case ARM
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/freebsd-10.2-release/lib/clang/libllvmarmcodegen/
H A DMakefile7 SRCDIR= lib/Target/ARM
/freebsd-10.2-release/contrib/llvm/include/llvm/MC/
H A DMCAsmInfo.h33 enum ExceptionsType { None, DwarfCFI, SjLj, ARM, Win64 }; enumerator in enum:llvm::ExceptionHandling::ExceptionsType
535 ExceptionsType == ExceptionHandling::ARM ||

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