Target/ARM/Thumb1RegisterInfo.cpp

16 #include "ARM.h"
50   if (ARM::tGPRRegClass.hasSubClassEq(RC))
51     return &ARM::tGPRRegClass;
58   return &ARM::tGPRRegClass;
78   BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
111     if (DestReg == ARM::SP) {
112       assert(BaseReg == ARM::SP && "Unexpected!");
113       LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
117       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
122       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
129     int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
132     if (Opc != ARM::tADDhirr)
134     if (DestReg == ARM::SP || isSub)
148   if (Opc == ARM::tADDrSPi) {
186   if (DestReg == BaseReg && BaseReg == ARM::SP) {
190     Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
192   } else if (!isSub && BaseReg == ARM::SP) {
199       ExtraOpc = ARM::tADDi3;
203     Opc = ARM::tADDrSPi;
211     if (DestReg == ARM::SP) {
212       Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
217       Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
225   unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
241       const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
247       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
268       bool isKill = BaseReg != ARM::SP;
277       if (Opc == ARM::tADDrSPi) {
284         Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
313   AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
319     const MCInstrDesc &MCID = TII.get(ARM::tRSB);
335   case ARM::tLDRspi:
336     return ARM::tLDRi;
338   case ARM::tSTRspi:
339     return ARM::tSTRi;
357   if (Opcode == ARM::tADDrSPi) {
363     if (FrameReg != ARM::SP) {
364       Opcode = ARM::tADDi3;
376       MI.setDesc(TII.get(ARM::tMOVr));
387       if (Opcode == ARM::tADDi3) {
415       if (Opcode == ARM::tADDi3) {
433       MI.setDesc(TII.get(ARM::tADDhirr));
444     unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
463       if (NewOpc != Opcode && FrameReg != ARM::SP)
474     if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
494   int Off = Offset; // ARM doesn't need the general 64-bit offsets
521   AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
522     .addReg(ARM::R12, RegState::Define)
535       if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
543       if (MO.getReg() == ARM::R12) {
551   AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
552     addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
571   unsigned FrameReg = ARM::SP;
593   if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
632     if (Opcode == ARM::tLDRspi) {
633       if (FrameReg == ARM::SP)
645     MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
653       VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
656       if (Opcode == ARM::tSTRspi) {
657         if (FrameReg == ARM::SP)
667       MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));