Target/ARM/A15SDOptimizer.cpp

12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
28 #include "ARM.h"
57       return "ARM A15 S->D optimizer";
152   unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
153                                            &ARM::DPRRegClass);
154   if (DReg != ARM::NoRegister) return ARM::ssub_1;
155   return ARM::ssub_0;
165   if (!MI) return ARM::ssub_0;
169   if (!MO) return ARM::ssub_0;
172                                     &ARM::SPRRegClass)) {
177     if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
178     return ARM::ssub_0;
276               EC->getOperand(1).getSubReg() == ARM::ssub_0) {
300                                           &ARM::SPRRegClass)) {
339   if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
343                                            &ARM::SPRRegClass))
346   if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
420     if (!usesRegClass(MO, &ARM::DPRRegClass) &&
421         !usesRegClass(MO, &ARM::QPRRegClass) &&
422         !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
436   unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
437                                                   &ARM::DPRRegClass);
441                          TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
472   unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
478     .addImm(ARM::dsub_0)
480     .addImm(ARM::dsub_1);
491   unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
495                          TII->get(ARM::VEXTd32), Out)
507   unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
523   unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
544   if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
545       MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
547                                          ARM::dsub_0, &ARM::DPRRegClass);
549                                          ARM::dsub_1, &ARM::DPRRegClass);
561   } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
567     assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
573       case ARM::ssub_0: Lane = 0; break;
574       case ARM::ssub_1: Lane = 1; break;
579     bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
580                    usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);