ARM/InstPrinter/ARMInstPrinter.cpp

1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
10 // This class prints an ARM MCInst to a .s file.
82   case ARM::HINT:
83   case ARM::tHINT:
84   case ARM::t2HINT:
92       if ((getAvailableFeatures() & ARM::HasV8Ops)) {
103     if (Opcode == ARM::t2HINT)
109   case ARM::MOVsr: {
132   case ARM::MOVsi: {
161   case ARM::STMDB_UPD:
162   case ARM::t2STMDB_UPD:
163     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
167       if (Opcode == ARM::t2STMDB_UPD)
176   case ARM::STR_PRE_IMM:
177     if (MI->getOperand(2).getReg() == ARM::SP &&
190   case ARM::LDMIA_UPD:
191   case ARM::t2LDMIA_UPD:
192     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
196       if (Opcode == ARM::t2LDMIA_UPD)
205   case ARM::LDR_POST_IMM:
206     if (MI->getOperand(2).getReg() == ARM::SP &&
219   case ARM::VSTMSDB_UPD:
220   case ARM::VSTMDDB_UPD:
221     if (MI->getOperand(0).getReg() == ARM::SP) {
232   case ARM::VLDMSIA_UPD:
233   case ARM::VLDMDIA_UPD:
234     if (MI->getOperand(0).getReg() == ARM::SP) {
244   case ARM::tLDMIA: {
270   case ARM::LDREXD: case ARM::STREXD:
271   case ARM::LDAEXD: case ARM::STLEXD:
272     const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
273     bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
282       NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
283         &MRI.getRegClass(ARM::GPRPairRegClassID)));
698   O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
758   printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
760   printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
797   if (getAvailableFeatures() & ARM::FeatureMClass) {
802     if (Opcode == ARM::t2MRS_M)
891     assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
892            "Expect ARM CPSR register!");
1307   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1308   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1320   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1321   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1371   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1372   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1416   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1417   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);