Lines Matching refs:ARM
1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
16 #include "ARM.h"
248 if (MO.getReg() == ARM::CPSR)
279 // Are we NEON in ARM mode and have a predicate operand? If so, I know
285 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
540 TII.get(ARM::VMOVSR), MoveReg)
550 TII.get(ARM::VMOVRS), MoveReg)
569 Opc = ARM::FCONSTD;
572 Opc = ARM::FCONSTS;
592 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
611 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
612 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
613 &ARM::GPRRegClass;
627 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
652 TII.get(ARM::t2LDRpci), DestReg)
656 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
658 TII.get(ARM::LDRcp), DestReg)
672 (const TargetRegisterClass*)&ARM::rGPRRegClass :
673 (const TargetRegisterClass*)&ARM::GPRRegClass;
690 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
693 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
696 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
724 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
732 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
733 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
740 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
758 TII.get(ARM::t2LDRi12), NewDestReg)
762 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
807 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
962 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
978 (const TargetRegisterClass*)&ARM::tGPRRegClass :
979 (const TargetRegisterClass*)&ARM::GPRRegClass;
981 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
1020 // ARM halfword load/stores and signed byte loads need an additional
1034 // ARM halfword load/stores and signed byte loads need an additional
1060 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1062 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1065 Opc = ARM::LDRBi12;
1067 Opc = ARM::LDRSB;
1071 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1079 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1081 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1083 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1086 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1094 Opc = ARM::t2LDRi8;
1096 Opc = ARM::t2LDRi12;
1098 Opc = ARM::LDRi12;
1100 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1108 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1109 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1111 Opc = ARM::VLDRS;
1122 Opc = ARM::VLDRD;
1142 TII.get(ARM::VMOVSR), MoveReg)
1179 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1180 (const TargetRegisterClass*)&ARM::GPRRegClass);
1181 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1191 StrOpc = ARM::t2STRBi8;
1193 StrOpc = ARM::t2STRBi12;
1195 StrOpc = ARM::STRBi12;
1204 StrOpc = ARM::t2STRHi8;
1206 StrOpc = ARM::t2STRHi12;
1208 StrOpc = ARM::STRH;
1218 StrOpc = ARM::t2STRi8;
1220 StrOpc = ARM::t2STRi12;
1222 StrOpc = ARM::STRi12;
1231 TII.get(ARM::VMOVRS), MoveReg)
1235 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1237 StrOpc = ARM::VSTRS;
1247 StrOpc = ARM::VSTRD;
1365 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1367 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1376 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1389 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1391 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1415 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1426 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1428 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1438 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1496 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1500 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1510 CmpOpc = ARM::t2CMPrr;
1512 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1515 CmpOpc = ARM::CMPrr;
1517 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1562 TII.get(ARM::FMSTAT)));
1581 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1583 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1584 (const TargetRegisterClass*)&ARM::GPRRegClass;
1591 .addImm(ARMPred).addReg(ARM::CPSR);
1608 unsigned Result = createResultReg(&ARM::DPRRegClass);
1610 TII.get(ARM::VCVTDS), Result)
1627 unsigned Result = createResultReg(&ARM::SPRRegClass);
1629 TII.get(ARM::VCVTSD), Result)
1668 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1669 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1694 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1695 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1747 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1755 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1756 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1758 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1760 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1762 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1769 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1773 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1841 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1844 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1847 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1859 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1888 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1891 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1894 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
2076 TII.get(ARM::VMOVRRD), VA.getLocReg())
2086 Addr.Base.Reg = ARM::SP;
2120 TII.get(ARM::VMOVDRR), ResultReg)
2201 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2224 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2235 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2237 return isThumb2 ? ARM::tBL : ARM::BL;
2257 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2473 // ARM calls don't take a predicate, but tBL / tBLX do.
2560 LdrOpc = ARM::t2LDRi12;
2561 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2563 LdrOpc = ARM::LDRi12;
2564 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2639 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2678 // ARM Thumb
2687 // - For ARM can never be PC.
2692 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2693 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2704 { // ARM Opc S Shift Imm
2705 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2706 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2707 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2708 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2709 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2710 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2713 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2714 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2715 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2716 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2717 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2718 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2722 { // ARM Opc S Shift Imm
2723 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2724 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2725 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2726 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2727 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2728 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2731 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2732 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2733 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2734 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2735 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2736 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2758 assert(ARM::KILL != Opc && "Invalid table entry");
2761 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2766 bool setsCPSR = &ARM::tGPRRegClass == RC;
2767 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2793 MIB.addReg(ARM::CPSR, RegState::Define);
2806 // On ARM, in general, integer casts don't involve legal types; this code
2842 unsigned Opc = ARM::MOVsr;
2853 Opc = ARM::MOVsi;
2861 if (Opc == ARM::MOVsr) {
2866 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2873 if (Opc == ARM::MOVsi)
2875 else if (Opc == ARM::MOVsr) {
2962 uint16_t Opc[2]; // ARM, Thumb.
2967 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2968 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2969 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2970 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2971 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
3029 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
3031 TII.get(ARM::t2LDRpci), DestReg1)
3033 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
3036 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
3038 DL, TII.get(ARM::LDRcp), DestReg1)
3040 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
3115 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3118 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3137 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3142 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.