Searched refs:zero (Results 26 - 47 of 47) sorted by relevance

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/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/src/
H A Dbcmcore_ircpoll.S126 beq v0, zero, 1f
168 nor t1,t1,zero
275 nor a0,a0,zero
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91280e/src/
H A Dbcm91280e_init.S137 sd zero,(t0)
139 sd zero,(t0)
194 nor t1, zero, zero
261 sd zero, 0(t0) # disable half.
267 ld zero, 0(t0)
446 bne t1,zero,1b
H A Dcpu1test.S136 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/src/
H A Dbcm91125e_init.S210 sd zero, R_MC_CS_START(t0)
211 sd zero, R_MC_CS_END(t0)
212 sd zero, R_MC_CS_INTERLEAVE(t0)
213 sd zero, R_MC_CS_ATTR(t0)
214 sd zero, R_MC_TEST_DATA(t0)
215 sd zero, R_MC_TEST_ECC(t0)
222 * to zero it.)
226 sd zero, R_MAC_ETHERNET_ADDR(t0)
325 sd zero,(t0)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/src/
H A Dbcm91125f_init.S198 sd zero, R_MC_CS_START(t0)
199 sd zero, R_MC_CS_END(t0)
200 sd zero, R_MC_CS_INTERLEAVE(t0)
201 sd zero, R_MC_CS_ATTR(t0)
202 sd zero, R_MC_TEST_DATA(t0)
203 sd zero, R_MC_TEST_ECC(t0)
210 * to zero it.)
214 sd zero, R_MAC_ETHERNET_ADDR(t0)
313 sd zero,(t0)
/broadcom-cfe-1.4.2/cfe/arch/mips/common/src/
H A Dlib_setjmp.S75 move v0,zero
H A Dlib_physio.S92 beq t0,zero,1f ; \
H A Dinit_mips.S355 move gp,zero # start with no GP.
382 sll k0,k0,3 # k0 bits now zero
517 bne k0,zero,have_ram
699 bge t0,zero,1f # and second entry if high bit set
812 1: SR zero,0(v0) # Zero one cacheline at a time
813 SR zero,(REGSIZE*1)(v0)
814 SR zero,(REGSIZE*2)(v0)
815 SR zero,(REGSIZE*3)(v0)
896 move v0,zero
1079 move a1,zero # A
[all...]
H A Dzipstart_entry.S120 SREG zero,XGR_ZERO(k1)
H A Dapientry.S489 lw zero,0(t0)
501 * a0 - flags (CFE_CACHE_xxx flags, or zero for a default)
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/
H A Dbcm1480_altcpu.S231 * Do this only for CPUs with non-zero processor IDs, possibly
281 beq t0,zero,2b # Loop till the bit is set
293 bne v0,zero,1b # Keep going if more secondary CPUs
349 bne v0,zero,1b # Keep going if more secondary CPUs
396 sd zero,R_CPU_STARTVECT(t1) # Reset address of CPU1
472 beq t0,zero,2b # Loop till the bit is set
508 move v0,zero
536 beq t0,zero,iscpu0 # go if on CPU0
677 move v0,zero /* success */
707 beq a0,zero,
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480b/src/
H A Dbcm91480b_init.S160 sd zero,(t0)
162 sd zero,(t0)
300 nor t1, zero, zero
367 sd zero, 0(t0) # disable half.
373 ld zero, 0(t0)
581 bne t1,zero,1b
H A Dcpu1test.S136 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/
H A Dsb1250_memcpy.S109 #define USE(x) lbu AT,x; xor zero, AT, zero
243 xor zero, AT, zero
244 xor zero, t0, zero
248 ADD zero, 1 # L1 NOP
249 xor zero, AT, zero
349 SUB mask, zero,
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/board/swarm/src/
H A Dswarm_init.S134 move t3, zero
395 move v0,zero # auto configure
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/
H A Dbcm91480ht_init.S137 sd zero,(t0)
139 sd zero,(t0)
226 nor t1, zero, zero
421 bne t1,zero,1b
H A Dcpu1test.S135 mtc0 zero,C0_COUNT
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_altcpu.S229 beq t0,zero,1b # Loop till the bit is set
341 sd zero,8(t1) # Reset address of CPU1 (2nd entry in table)
401 move v0,zero
430 beq t0,zero,iscpu0 # go if on CPU0
597 move v0,zero /* success */
680 beq t0,zero,1b # Loop till the bit is set
698 * zero, so clear that first).
768 * table below will be the zero, causing
779 beq t1,zero,loop_forever
/broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/
H A Dsentosa_init.S147 nor t1, zero, zero
/broadcom-cfe-1.4.2/cfe/verif/
H A Dvapi.S163 beq RECPTR,zero,label ; \
315 beq t0,zero,nolog
336 beq t0,zero,1f # skip if not in reset
506 sd zero,vapi_logover
608 1: beq k0,zero,2f
669 move a2,zero # Counts how many we write
674 beq t0,zero,2f
676 beq t0,zero,3f # skip if no flags set
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/include/
H A Dsbmips32.h132 #define zero $0 macro
298 /* define a zero-fill common block (BSS if not overridden) with a global name */
302 /* define a zero-fill common block (BSS if not overridden) with a local name */
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/include/
H A Dsbmips.h182 #define zero $0 macro
628 /* define a zero-fill common block (BSS if not overridden) with a global name */
632 /* define a zero-fill common block (BSS if not overridden) with a local name */

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