1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * MIPS32 CPU definitions File: sbmips32.h 5 * 6 * This module contains constants and macros specific to the 7 * Broadcom MIPS32 core. In addition to generic MIPS32, it 8 * includes definitions for the MIP32-01 and MIPS3302 OCP cores 9 * for the Silicon Backplane. 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48#ifndef _SB_MIPS32_H 49#define _SB_MIPS32_H 50 51/* ********************************************************************* 52 * Configure language 53 ********************************************************************* */ 54 55#if defined(__ASSEMBLER__) 56#define _ATYPE_ 57#define _ATYPE32_ 58#else 59#define _ATYPE_ (__SIZE_TYPE__) 60#define _ATYPE32_ (int) 61#endif 62 63 64/* ********************************************************************* 65 * Bitfield macros 66 ********************************************************************* */ 67 68/* Make a mask for 1 bit at position 'n' */ 69 70#define _MM_MAKEMASK1(n) (1 << (n)) 71 72/* Make a mask for 'v' bits at position 'n' */ 73 74#define _MM_MAKEMASK(v,n) (((1<<(v))-1) << (n)) 75 76/* Make a value at 'v' at bit position 'n' */ 77 78#define _MM_MAKEVALUE(v,n) ((v) << (n)) 79 80/* Retrieve a value from 'v' at bit position 'n' with 'm' mask bits */ 81 82#define _MM_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 83 84 85 86/* ********************************************************************* 87 * 32-bit MIPS Address Spaces 88 ********************************************************************* */ 89 90#ifdef __ASSEMBLER__ 91#define _ACAST32_ 92#else 93#define _ACAST32_ _ATYPE_ _ATYPE32_ /* widen if necessary */ 94#endif 95 96/* 32-bit address map */ 97#define UBASE 0x00000000 /* user+ mapped */ 98#define USIZE 0x80000000 99#define K0BASE (_ACAST32_ 0x80000000) /* kernel unmapped cached */ 100#define K0SIZE 0x20000000 101#define K1BASE (_ACAST32_ 0xa0000000) /* kernel unmapped uncached */ 102#define K1SIZE 0x20000000 103#define K2BASE (_ACAST32_ 0xc0000000) /* kernel mapped */ 104#define K2SIZE 0x40000000 105 106#define GEN_VECT (_ACAST32_ 0x80000080) 107#define UTLB_VECT (_ACAST32_ 0x80000000) 108 109/* ********************************************************************* 110 * Address space coercion macros 111 ********************************************************************* */ 112 113#define PHYS_TO_K0(pa) (K0BASE | (pa)) 114#define PHYS_TO_K1(pa) (K1BASE | (pa)) 115#define K0_TO_PHYS(va) ((va) & (K0SIZE-1)) 116#define K1_TO_PHYS(va) ((va) & (K1SIZE-1)) 117#define K0_TO_K1(va) ((va) | K1SIZE) 118#define K1_TO_K0(va) ((va) & ~K1SIZE) 119 120 121#if !defined(__ASSEMBLER__) 122#define mips_wbflush() __asm__ __volatile__ ("sync" : : : "memory") 123#define ISK0SEG(va) ((va) >= K0BASE && (va) <= (K0BASE + K0SIZE - 1)) 124#define ISK1SEG(va) ((va) >= K1BASE && (va) <= (K1BASE + K1SIZE - 1)) 125#endif 126 127/* ********************************************************************* 128 * Register aliases 129 ********************************************************************* */ 130 131#if defined(__ASSEMBLER__) 132#define zero $0 133#define AT $1 /* assembler temporaries */ 134#define v0 $2 /* value holders */ 135#define v1 $3 136#define a0 $4 /* arguments */ 137#define a1 $5 138#define a2 $6 139#define a3 $7 140#define t0 $8 /* temporaries */ 141#define t1 $9 142#define t2 $10 143#define t3 $11 144#define t4 $12 145#define t5 $13 146#define t6 $14 147#define t7 $15 148#define s0 $16 /* saved registers */ 149#define s1 $17 150#define s2 $18 151#define s3 $19 152#define s4 $20 153#define s5 $21 154#define s6 $22 155#define s7 $23 156#define t8 $24 /* temporaries */ 157#define t9 $25 158#define k0 $26 /* kernel registers */ 159#define k1 $27 160#define gp $28 /* global pointer */ 161#define sp $29 /* stack pointer */ 162#define s8 $30 /* saved register */ 163#define fp $30 /* frame pointer */ 164#define ra $31 /* return address */ 165#endif 166 167/* ********************************************************************* 168 * CP0 Registers 169 ********************************************************************* */ 170 171#if defined(__ASSEMBLER__) 172#define C0_INX $0 /* CP0: TLB Index */ 173#define C0_RAND $1 /* CP0: TLB Random */ 174#define C0_TLBLO0 $2 /* CP0: TLB EntryLo0 */ 175#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ 176#define C0_TLBLO1 $3 /* CP0: TLB EntryLo1 */ 177#define C0_CTEXT $4 /* CP0: Context */ 178#define C0_PGMASK $5 /* CP0: TLB PageMask */ 179#define C0_WIRED $6 /* CP0: TLB Wired */ 180#define C0_BADVADDR $8 /* CP0: Bad Virtual Address */ 181#define C0_COUNT $9 /* CP0: Count */ 182#define C0_TLBHI $10 /* CP0: TLB EntryHi */ 183#define C0_COMPARE $11 /* CP0: Compare */ 184#define C0_SR $12 /* CP0: Processor Status */ 185#define C0_STATUS C0_SR /* CP0: Processor Status */ 186#define C0_CAUSE $13 /* CP0: Exception Cause */ 187#define C0_EPC $14 /* CP0: Exception PC */ 188#define C0_PRID $15 /* CP0: Processor Revision Indentifier */ 189#define C0_CONFIG $16 /* CP0: Config */ 190#define C0_LLADDR $17 /* CP0: LLAddr */ 191#define C0_WATCHLO $18 /* CP0: WatchpointLo */ 192#define C0_WATCHHI $19 /* CP0: WatchpointHi */ 193#define C0_BRCMCFG $22 /* CP0: Broadcom Config (BMIPS-330x) */ 194#define C0_PERFCONT $25 /* CP0: Performance counters */ 195#define C0_ECC $26 /* CP0: ECC */ 196#define C0_CACHEERR $27 /* CP0: CacheErr */ 197#define C0_TAGLO $28 /* CP0: TagLo */ 198#define C0_TAGHI $29 /* CP0: TagHi */ 199#define C0_ERREPC $30 /* CP0: ErrorEPC */ 200 201#else 202#define C0_INX 0 /* CP0: TLB Index */ 203#define C0_RAND 1 /* CP0: TLB Random */ 204#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */ 205#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ 206#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */ 207#define C0_CTEXT 4 /* CP0: Context */ 208#define C0_PGMASK 5 /* CP0: TLB PageMask */ 209#define C0_WIRED 6 /* CP0: TLB Wired */ 210#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */ 211#define C0_COUNT 9 /* CP0: Count */ 212#define C0_TLBHI 10 /* CP0: TLB EntryHi */ 213#define C0_COMPARE 11 /* CP0: Compare */ 214#define C0_SR 12 /* CP0: Processor Status */ 215#define C0_STATUS C0_SR /* CP0: Processor Status */ 216#define C0_CAUSE 13 /* CP0: Exception Cause */ 217#define C0_EPC 14 /* CP0: Exception PC */ 218#define C0_PRID 15 /* CP0: Processor Revision Indentifier */ 219#define C0_CONFIG 16 /* CP0: Config */ 220#define C0_LLADDR 17 /* CP0: LLAddr */ 221#define C0_WATCHLO 18 /* CP0: WatchpointLo */ 222#define C0_WATCHHI 19 /* CP0: WatchpointHi */ 223#define C0_BRCMCFG 22 /* CP0: Broadcom Config (BMIPS3302) */ 224#define C0_PERFCONT 25 /* CP0: Performance counters */ 225#define C0_ECC 26 /* CP0: ECC */ 226#define C0_CACHEERR 27 /* CP0: CacheErr */ 227#define C0_TAGLO 28 /* CP0: TagLo */ 228#define C0_TAGHI 29 /* CP0: TagHi */ 229#define C0_ERREPC 30 /* CP0: ErrorEPC */ 230 231#endif 232 233/* Aliases to match MIPS manuals. */ 234#define C0_INDEX C0_INX 235#define C0_RANDOM C0_RAND 236#define C0_ENTRYLO0 C0_TLBLO0 237#define C0_ENTRYLO1 C0_TLBLO1 238#define C0_CONTEXT C0_CTEXT 239#define C0_PAGEMASK C0_PGMASK 240#define C0_ENTRYHI C0_TLBHI 241#define C0_STATUS C0_SR 242#define C0_PERFCNT C0_PERFCONT 243#define C0_ERROREPC C0_ERREPC 244 245/* ********************************************************************* 246 * CP1 (floating point) control registers 247 ********************************************************************* */ 248 249#define FPA_IRR 0 /* CP1: Implementation/Revision */ 250#define FPA_CSR 31 /* CP1: Control/Status */ 251 252/* ********************************************************************* 253 * Macros for generating assembly language routines 254 ********************************************************************* */ 255 256#if defined(__ASSEMBLER__) 257 258/* global leaf function (does not call other functions) */ 259#define LEAF(name) \ 260 .globl name; \ 261 .ent name; \ 262name: 263 264/* global alternate entry to (local or global) leaf function */ 265#define XLEAF(name) \ 266 .globl name; \ 267 .aent name; \ 268name: 269 270/* end of a global function */ 271#define END(name) \ 272 .size name,.-name; \ 273 .end name 274 275/* local leaf function (does not call other functions) */ 276#define SLEAF(name) \ 277 .ent name; \ 278name: 279 280/* local alternate entry to (local or global) leaf function */ 281#define SXLEAF(name) \ 282 .aent name; \ 283name: 284 285/* end of a local function */ 286#define SEND(name) \ 287 END(name) 288 289/* define & export a symbol */ 290#define EXPORT(name) \ 291 .globl name; \ 292name: 293 294/* import a symbol */ 295#define IMPORT(name, size) \ 296 .extern name,size 297 298/* define a zero-fill common block (BSS if not overridden) with a global name */ 299#define COMM(name,size) \ 300 .comm name,size 301 302/* define a zero-fill common block (BSS if not overridden) with a local name */ 303#define LCOMM(name,size) \ 304 .lcomm name,size 305 306#endif 307 308 309/* Floating-Point Control register bits */ 310#define CSR_C 0x00800000 311#define CSR_EXC 0x0003f000 312#define CSR_EE 0x00020000 313#define CSR_EV 0x00010000 314#define CSR_EZ 0x00008000 315#define CSR_EO 0x00004000 316#define CSR_EU 0x00002000 317#define CSR_EI 0x00001000 318#define CSR_TV 0x00000800 319#define CSR_TZ 0x00000400 320#define CSR_TO 0x00000200 321#define CSR_TU 0x00000100 322#define CSR_TI 0x00000080 323#define CSR_SV 0x00000040 324#define CSR_SZ 0x00000020 325#define CSR_SO 0x00000010 326#define CSR_SU 0x00000008 327#define CSR_SI 0x00000004 328#define CSR_RM 0x00000003 329 330/* Status Register */ 331#define M_SR_CUMASK _MM_MAKEMASK(4,28) /* coprocessor usable bits */ 332#define M_SR_CU3 _MM_MAKEMASK1(31) /* coprocessor 3 usable */ 333#define M_SR_CU2 _MM_MAKEMASK1(30) /* coprocessor 2 usable */ 334#define M_SR_CU1 _MM_MAKEMASK1(29) /* coprocessor 1 usable */ 335#define M_SR_CU0 _MM_MAKEMASK1(28) /* coprocessor 0 usable */ 336 337#define M_SR_RP _MM_MAKEMASK1(27) /* reduced power mode */ 338#define M_SR_RE _MM_MAKEMASK1(25) /* reverse endian */ 339#define M_SR_BEV _MM_MAKEMASK1(22) /* boot exception vectors */ 340#define M_SR_TS _MM_MAKEMASK1(21) /* TLB is shut down */ 341#define M_SR_SR _MM_MAKEMASK1(20) /* soft reset */ 342#define M_SR_NMI _MM_MAKEMASK1(19) /* nonmaskable interrupt */ 343 344#define S_SR_IMMASK 8 345#define M_SR_IMMASK _MM_MAKEMASK(9,S_SR_IMMASK) 346 347#define M_SR_IM8 _MM_MAKEMASK1(16) /* Broadcom extension */ 348#define M_SR_IM7 _MM_MAKEMASK1(15) /* hardware interrupt masks */ 349#define M_SR_IM6 _MM_MAKEMASK1(14) 350#define M_SR_IM5 _MM_MAKEMASK1(13) 351#define M_SR_IM4 _MM_MAKEMASK1(12) 352#define M_SR_IM3 _MM_MAKEMASK1(11) 353#define M_SR_IM2 _MM_MAKEMASK1(10) 354#define M_SR_IM1 _MM_MAKEMASK1(9) /* software interrupt masks */ 355#define M_SR_IM0 _MM_MAKEMASK1(8) 356 357#define S_SR_KSU 3 /* base operating mode mode */ 358#define M_SR_KSU _MM_MAKEMASK(2,S_SR_KSU) 359#define V_SR_KSU(x) _MM_MAKEVALUE(x,S_SR_KSU) 360#define G_SR_KSU(x) _MM_GETVALUE(x,S_SR_KSU,M_SR_KSU) 361#define K_SR_KSU_KERNEL 0 362#define K_SR_KSU_SUPR 1 363#define K_SR_KSU_USER 2 364 365#define M_SR_UM _MM_MAKEMASK1(4) 366#define M_SR_ERL _MM_MAKEMASK1(2) 367#define M_SR_EXL _MM_MAKEMASK1(1) 368#define M_SR_IE _MM_MAKEMASK1(0) 369 370/* 371 * Cause Register 372 */ 373#define M_CAUSE_BD _MM_MAKEMASK1(31) /* exception in BD slot */ 374 375#define S_CAUSE_CE 28 /* coprocessor error */ 376#define M_CAUSE_CE _MM_MAKEMASK(2,S_CAUSE_CE) 377#define V_CAUSE_CE(x) _MM_MAKEVALUE(x,S_CAUSE_CE) 378#define G_CAUSE_CE(x) _MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE) 379 380#define M_CAUSE_IV _MM_MAKEMASK1(23) /* special interrupt */ 381#define M_CAUSE_WP _MM_MAKEMASK1(22) /* watch interrupt deferred */ 382 383#define S_CAUSE_IPMASK 8 384#define M_CAUSE_IPMASK _MM_MAKEMASK(9,S_CAUSE_IPMASK) 385 386#define M_CAUSE_IP8 _MM_MAKEMASK1(16) /* Broadcom extension */ 387#define M_CAUSE_IP7 _MM_MAKEMASK1(15) /* hardware interrupts */ 388#define M_CAUSE_IP6 _MM_MAKEMASK1(14) 389#define M_CAUSE_IP5 _MM_MAKEMASK1(13) 390#define M_CAUSE_IP4 _MM_MAKEMASK1(12) 391#define M_CAUSE_IP3 _MM_MAKEMASK1(11) 392#define M_CAUSE_IP2 _MM_MAKEMASK1(10) 393#define M_CAUSE_SW1 _MM_MAKEMASK1(9) /* software interrupts */ 394#define M_CAUSE_SW0 _MM_MAKEMASK1(8) 395 396#define S_CAUSE_EXC 2 397#define M_CAUSE_EXC _MM_MAKEMASK(5,S_CAUSE_EXC) 398#define V_CAUSE_EXC(x) _MM_MAKEVALUE(x,S_CAUSE_EXC) 399#define G_CAUSE_EXC(x) _MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC) 400 401/* Exception Code */ 402#define K_CAUSE_EXC_INT 0 /* External interrupt */ 403#define K_CAUSE_EXC_MOD 1 /* TLB modification */ 404#define K_CAUSE_EXC_TLBL 2 /* TLB miss (Load or Ifetch) */ 405#define K_CAUSE_EXC_TLBS 3 /* TLB miss (Save) */ 406#define K_CAUSE_EXC_ADEL 4 /* Address error (Load or Ifetch) */ 407#define K_CAUSE_EXC_ADES 5 /* Address error (Save) */ 408#define K_CAUSE_EXC_IBE 6 /* Bus error (Ifetch) */ 409#define K_CAUSE_EXC_DBE 7 /* Bus error (data load or store) */ 410#define K_CAUSE_EXC_SYS 8 /* System call */ 411#define K_CAUSE_EXC_BP 9 /* Break point */ 412#define K_CAUSE_EXC_RI 10 /* Reserved instruction */ 413#define K_CAUSE_EXC_CPU 11 /* Coprocessor unusable */ 414#define K_CAUSE_EXC_OVF 12 /* Arithmetic overflow */ 415#define K_CAUSE_EXC_TRAP 13 /* Trap exception */ 416#define K_CAUSE_EXC_FPE 15 /* Floating Point Exception */ 417#define K_CAUSE_EXC_CP2 16 /* Cp2 Exception */ 418#define K_CAUSE_EXC_WATCH 23 /* Watchpoint exception */ 419 420#define K_NTLBENTRIES 32 421 422#define HI_HALF(x) ((x) >> 16) 423#define LO_HALF(x) ((x) & 0xffff) 424 425/* FPU stuff */ 426 427#if defined(__ASSEMBLER__) 428#define C1_CSR $31 429#define C1_FRID $0 430#else 431#define C1_CSR 31 432#define C1_FRID 0 433#endif 434 435#define S_FCSR_CAUSE 12 436#define M_FCSR_CAUSE _MM_MAKEMASK(5,S_FCSR_CAUSE) 437#define V_FCSR_CAUSE(x) _MM_MAKEVALUE(x,S_FCSR_CAUSE) 438#define G_FCSR_CAUSE(x) _MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE) 439 440#define S_FCSR_ENABLES 7 441#define M_FCSR_ENABLES _MM_MAKEMASK(5,S_FCSR_ENABLES) 442#define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES) 443#define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES) 444 445#define S_FCSR_FLAGS 2 446#define M_FCSR_FLAGS _MM_MAKEMASK(5,S_FCSR_FLAGS) 447#define V_FCSR_FLAGS(x) _MM_MAKEVALUE(x,S_FCSR_FLAGS) 448#define G_FCSR_FLAGS(x) _MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS) 449 450 451/* 452 * MIPS32 Config Register (select 0) 453 */ 454#define M_CFG_CFG1 _MM_MAKEMASK1(31) /* config1 select1 is impl */ 455#define M_CFG_BE _MM_MAKEMASK1(15) /* big-endian mode */ 456 457#define S_CFG_AT 13 /* Architecture Type */ 458#define M_CFG_AT _MM_MAKEMASK(2,S_CFG_AT) 459#define V_CFG_AT(x) _MM_MAKEVALUE(x,S_CFG_AT) 460#define G_CFG_AT(x) _MM_GETVALUE(x,S_CFG_AT,M_CFG_AT) 461#define K_CFG_AT_MIPS32 0 462#define K_CFG_AT_MIPS64_32 1 463#define K_CFG_AT_MIPS64 2 464 465#define S_CFG_AR 10 /* Architecture Revision */ 466#define M_CFG_AR _MM_MAKEMASK(3,S_CFG_AR) 467#define V_CFG_AR(x) _MM_MAKEVALUE(x,S_CFG_AR) 468#define G_CFG_AR(x) _MM_GETVALUE(x,S_CFG_AR,M_CFG_AR) 469#define K_CFG_AR_REV1 0 470 471#define S_CFG_MMU 7 /* MMU Type */ 472#define M_CFG_MMU _MM_MAKEMASK(3,S_CFG_MMU) 473#define V_CFG_MMU(x) _MM_MAKEVALUE(x,S_CFG_MMU) 474#define G_CFG_MMU(x) _MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU) 475#define K_CFG_MMU_NONE 0 476#define K_CFG_MMU_TLB 1 477#define K_CFG_MMU_BAT 2 478#define K_CFG_MMU_FIXED 3 479 480#define S_CFG_K0COH 0 /* K0seg coherency */ 481#define M_CFG_K0COH _MM_MAKEMASK(3,S_CFG_K0COH) 482#define V_CFG_K0COH(x) _MM_MAKEVALUE(x,S_CFG_K0COH) 483#define G_CFG_K0COH(x) _MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH) 484#define K_CFG_K0COH_UNCACHED 2 485#define K_CFG_K0COH_CACHEABLE 3 486#define K_CFG_K0COH_COHERENT 5 487 488/* 489 * MIPS32 Config Register (select 1) 490 */ 491 492#define M_CFG_CFG2 _MM_MAKEMASK1(31) /* config2 select2 is impl */ 493 494#define S_CFG_MMUSIZE 25 495#define M_CFG_MMUSIZE _MM_MAKEMASK(6,S_CFG_MMUSIZE) 496 497#define S_CFG_IS 22 498#define M_CFG_IS _MM_MAKEMASK(3,S_CFG_IS) 499#define V_CFG_IS(x) _MM_MAKEVALUE(x,S_CFG_IS) 500#define G_CFG_IS(x) _MM_GETVALUE(x,S_CFG_IS,M_CFG_IS) 501 502#define S_CFG_IL 19 503#define M_CFG_IL _MM_MAKEMASK(3,S_CFG_IL) 504#define V_CFG_IL(x) _MM_MAKEVALUE(x,S_CFG_IL) 505#define G_CFG_IL(x) _MM_GETVALUE(x,S_CFG_IL,M_CFG_IL) 506 507#define S_CFG_IA 16 508#define M_CFG_IA _MM_MAKEMASK(3,S_CFG_IA) 509#define V_CFG_IA(x) _MM_MAKEVALUE(x,S_CFG_IA) 510#define G_CFG_IA(x) _MM_GETVALUE(x,S_CFG_IA,M_CFG_IA) 511 512#define S_CFG_DS 13 513#define M_CFG_DS _MM_MAKEMASK(3,S_CFG_DS) 514#define V_CFG_DS(x) _MM_MAKEVALUE(x,S_CFG_DS) 515#define G_CFG_DS(x) _MM_GETVALUE(x,S_CFG_DS,M_CFG_DS) 516 517#define S_CFG_DL 10 518#define M_CFG_DL _MM_MAKEMASK(3,S_CFG_DL) 519#define V_CFG_DL(x) _MM_MAKEVALUE(x,S_CFG_DL) 520#define G_CFG_DL(x) _MM_GETVALUE(x,S_CFG_DL,M_CFG_DL) 521 522#define S_CFG_DA 7 523#define M_CFG_DA _MM_MAKEMASK(3,S_CFG_DA) 524#define V_CFG_DA(x) _MM_MAKEVALUE(x,S_CFG_DA) 525#define G_CFG_DA(x) _MM_GETVALUE(x,S_CFG_DA,M_CFG_DA) 526 527#define M_CFG_PC _MM_MAKEMASK1(4) /* perf ctrs present */ 528#define M_CFG_WR _MM_MAKEMASK1(3) /* watch regs present */ 529#define M_CFG_CA _MM_MAKEMASK1(2) /* MIPS16 present */ 530#define M_CFG_EP _MM_MAKEMASK1(1) /* EJTAG present */ 531#define M_CFG_FP _MM_MAKEMASK1(0) /* FPU present */ 532 533 534 535/* 536 * Primary Cache TagLo 537 */ 538 539#define S_TAGLO_PTAG 8 540#define M_TAGLO_PTAG _MM_MAKEMASK(56,S_TAGLO_PTAG) 541 542#define S_TAGLO_PSTATE 6 543#define M_TAGLO_PSTATE _MM_MAKEMASK(2,S_TAGLO_PSTATE) 544#define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE) 545#define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE) 546#define K_TAGLO_PSTATE_INVAL 0 547#define K_TAGLO_PSTATE_SHARED 1 548#define K_TAGLO_PSTATE_CLEAN_EXCL 2 549#define K_TAGLO_PSTATE_DIRTY_EXCL 3 550 551#define M_TAGLO_LOCK _MM_MAKEMASK1(5) 552#define M_TAGLO_PARITY _MM_MAKEMASK1(0) 553 554 555/* 556 * CP0 CacheErr register 557 */ 558#define M_CERR_DATA _MM_MAKEMASK1(31) /* err in D space */ 559#define M_CERR_SCACHE _MM_MAKEMASK1(30) /* err in l2, not l1 */ 560#define M_CERR_DERR _MM_MAKEMASK1(29) /* data error */ 561#define M_CERR_TERR _MM_MAKEMASK1(28) /* tag error */ 562#define M_CERR_EXTRQ _MM_MAKEMASK1(27) /* external req caused err */ 563#define M_CERR_BPAR _MM_MAKEMASK1(26) /* bus parity err */ 564#define M_CERR_ADATA _MM_MAKEMASK1(25) /* additional data */ 565#define M_CERR_IDX _MM_MAKEMASK(22,0) 566 567 568 569/* 570 * Primary Cache operations 571 */ 572#define Index_Invalidate_I 0x0 /* 0 0 */ 573#define Index_Writeback_Inv_D 0x1 /* 0 1 */ 574#define Index_Invalidate_SI 0x2 /* 0 2 */ 575#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ 576#define Index_Load_Tag_I 0x4 /* 1 0 */ 577#define Index_Load_Tag_D 0x5 /* 1 1 */ 578#define Index_Load_Tag_SI 0x6 /* 1 2 */ 579#define Index_Load_Tag_SD 0x7 /* 1 3 */ 580#define Index_Store_Tag_I 0x8 /* 2 0 */ 581#define Index_Store_Tag_D 0x9 /* 2 1 */ 582#define Index_Store_Tag_SI 0xA /* 2 2 */ 583#define Index_Store_Tag_SD 0xB /* 2 3 */ 584#define Create_Dirty_Exc_D 0xD /* 3 1 */ 585#define Create_Dirty_Exc_SD 0xF /* 3 3 */ 586#define Hit_Invalidate_I 0x10 /* 4 0 */ 587#define Hit_Invalidate_D 0x11 /* 4 1 */ 588#define Hit_Invalidate_SI 0x12 /* 4 2 */ 589#define Hit_Invalidate_SD 0x13 /* 4 3 */ 590#define Fill_I 0x14 /* 5 0 */ 591#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ 592#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ 593#define Hit_Writeback_I 0x18 /* 6 0 */ 594#define Hit_Writeback_D 0x19 /* 6 1 */ 595#define Hit_Writeback_SD 0x1B /* 6 3 */ 596#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ 597#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ 598 599/* Watchpoint Register */ 600#define M_WATCH_PA 0xfffffff8 601#define M_WATCH_R 0x00000002 602#define M_WATCH_W 0x00000001 603 604 605/* TLB entries */ 606#define M_TLBHI_ASID _MM_MAKEMASK(8,0) 607#define M_TLBHI_VPN2 _MM_MAKEMASK(27,13) 608 609#define M_TLBLO_G _MM_MAKEMASK1(0) 610#define M_TLBLO_V _MM_MAKEMASK1(1) 611#define M_TLBLO_D _MM_MAKEMASK1(2) 612 613#define S_TLBLO_CALG 3 614#define M_TLBLO_CALG _MM_MAKEMASK(3,S_TLBLO_CALG) 615#define V_TLBLO_CALG(x) _MM_MAKEVALUE(x,S_TLBLO_CALG) 616#define G_TLBLO_CALG(x) _MM_GETVALUE(x,S_TLBLO_CALG,M_TLBLO_CALG) 617 618#define K_CALG_COH_EXCL1_NOL2 0 619#define K_CALG_COH_SHRL1_NOL2 1 620#define K_CALG_UNCACHED 2 621#define K_CALG_NONCOHERENT 3 622#define K_CALG_COH_EXCL 4 623#define K_CALG_COH_SHAREABLE 5 624#define K_CALG_NOTUSED 6 625#define K_CALG_UNCACHED_ACCEL 7 626 627#define S_TLBLO_PFNMASK 6 628#define M_TLBLO_PFNMASK _MM_MAKEMASK(24,S_TLBLO_PFNMASK) 629#define V_TLBLO_PFNMASK(x) _MM_MAKEVALUE(x,S_TLBLO_PFNMASK) 630#define G_TLBLO_PFNMASK(x) _MM_GETVALUE(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK) 631 632 633/* 634 * The following Broadcom Custom CP0 Registers appear in the Broadcom 635 * BMIPS330x MIPS32 core. 636 */ 637 638/* 639 * Broadcom PLLConfig1 Register (22, select 1) 640 */ 641 642#define S_PLLCFG1_MC 10 /* SoftMIPSPLLCfg */ 643#define M_PLLCFG1_MC _MM_MAKEMASK(22,S_PLLCFG1_MC) 644#define V_PLLCFG1_MC(x) _MM_MAKEVALUE(x,S_PLLCFG1_MC) 645#define G_PLLCFG1_MC(x) _MM_GETVALUE(x,S_PLLCFG1_MC,M_PLLCFG1_MC) 646 647#define S_PLLCFG1_BC 5 /* SoftISBPLLCfg */ 648#define M_PLLCFG1_BC _MM_MAKEMASK(5,S_PLLCFG1_BC) 649#define V_PLLCFG1_BC(x) _MM_MAKEVALUE(x,S_PLLCFG1_BC) 650#define G_PLLCFG1_BC(x) _MM_GETVALUE(x,S_PLLCFG1_BC,M_PLLCFG1_BC) 651 652#define S_PLLCFG1_PC 0 /* SoftRefPLLCfg */ 653#define M_PLLCFG1_PC _MM_MAKEMASK(5,S_PLLCFG1_PC) 654#define V_PLLCFG1_PC(x) _MM_MAKEVALUE(x,S_PLLCFG1_PC) 655#define G_PLLCFG1_PC(x) _MM_GETVALUE(x,S_PLLCFG1_PC,M_PLLCFG1_PC) 656 657/* 658 * Broadcom PLLConfig2 Register (22, select 2) 659 */ 660 661#define M_PLLCFG2_CR _MM_MAKEMASK1(23) /* Soft1to1ClkRatio */ 662 663#define S_PLLCFG2_UC 15 /* SoftUSBxPLLCfg */ 664#define M_PLLCFG2_UC _MM_MAKEMASK(8,S_PLLCFG2_UC) 665#define V_PLLCFG2_UC(x) _MM_MAKEVALUE(x,S_PLLCFG2_UC) 666#define G_PLLCFG2_UC(x) _MM_GETVALUE(x,S_PLLCFG2_UC,M_PLLCFG2_UC) 667 668#define S_PLLCFG2_IC 7 /* SoftIDExPLLCfg */ 669#define M_PLLCFG2_IC _MM_MAKEMASK(8,S_PLLCFG2_IC) 670#define V_PLLCFG2_IC(x) _MM_MAKEVALUE(x,S_PLLCFG2_IC) 671#define G_PLLCFG2_IC(x) _MM_GETVALUE(x,S_PLLCFG2_IC,M_PLLCFG2_IC) 672 673#define M_PLLCFG2_BE _MM_MAKEMASK1(6) /* ISBxSoftCfgEnable */ 674#define M_PLLCFG2_UE _MM_MAKEMASK1(5) /* USBxSoftCfgEnable */ 675#define M_PLLCFG2_IE _MM_MAKEMASK1(4) /* IDExSoftCfgEnable */ 676#define M_PLLCFG2_CA _MM_MAKEMASK1(3) /* CfgActive */ 677#define M_PLLCFG2_CF _MM_MAKEMASK1(2) /* RefSoftCfgEnable */ 678#define M_PLLCFG2_CI _MM_MAKEMASK1(1) /* ISBSoftCfgEnable */ 679#define M_PLLCFG2_CC _MM_MAKEMASK1(0) /* MIPSSoftCfgEnable */ 680 681/* 682 * Broadcom ClkSync Register (22, select 3) 683 */ 684 685#define S_CLKSYNC_CH 16 /* SoftClkCfgHigh */ 686#define M_CLKSYNC_CH _MM_MAKEMASK(16,S_CLKSYNC_CH) 687#define V_CLKSYNC_CH(x) _MM_MAKEVALUE(x,S_CLKSYNC_CH) 688#define G_CLKSYNC_CH(x) _MM_GETVALUE(x,S_CLKSYNC_CH,M_CLKSYNC_CH) 689 690#define S_CLKSYNC_CL 0 /* SoftClkCfgLow */ 691#define M_CLKSYNC_CL _MM_MAKEMASK(16,S_CLKSYNC_CL) 692#define V_CLKSYNC_CL(x) _MM_MAKEVALUE(x,S_CLKSYNC_CL) 693#define G_CLKSYNC_CL(x) _MM_GETVALUE(x,S_CLKSYNC_CL,M_CLKSYNC_CL) 694 695/* 696 * Broadcom ISBxPLLConfig3 Register (22, select 4) 697 */ 698 699#define S_PLLCFG3_AR 23 /* AsyncClkRatio */ 700#define M_PLLCFG3_AR _MM_MAKEMASK(2,S_PLLCFG3_AR) 701#define V_PLLCFG3_AR(x) _MM_MAKEVALUE(x,S_PLLCFG3_AR) 702#define G_PLLCFG3_AR(x) _MM_GETVALUE(x,S_PLLCFG3_AR,M_PLLCFG3_AR) 703 704#define M_PLLCFG3_SM _MM_MAKEMASK1(22) /* SyncMode */ 705 706#define S_PLLCFG3_IC 0 /* SoftISBxPLLCfg */ 707#define M_PLLCFG3_IC _MM_MAKEMASK(22,S_PLLCFG3_IC) 708#define V_PLLCFG3_IC(x) _MM_MAKEVALUE(x,S_PLLCFG3_IC) 709#define G_PLLCFG3_IC(x) _MM_GETVALUE(x,S_PLLCFG3_IC,M_PLLCFG3_IC) 710 711/* 712 * Broadcom BRCMRstConfig Register (22, select 5) 713 */ 714 715#define M_RSTCFG_SR _MM_MAKEMASK1(18) /* SSMR */ 716#define M_RSTCFG_DT _MM_MAKEMASK1(16) /* BHTD */ 717 718#define S_RSTCFG_RS 8 /* RStSt */ 719#define M_RSTCFG_RS _MM_MAKEMASK(5,S_RSTCFG_RS) 720#define V_RSTCFG_RS(x) _MM_MAKEVALUE(x,S_RSTCFG_RS) 721#define G_RSTCFG_RS(x) _MM_GETVALUE(x,S_RSTCFG_RS,M_RSTCFG_RS) 722#define K_RST_OTHER 0x00 723#define K_RST_SH 0x01 724#define K_RST_SS 0x02 725#define K_RST_EJTAG 0x04 726#define K_RST_WDOG 0x08 727#define K_RST_CRC 0x10 728 729#define M_RSTCFG_CR _MM_MAKEMASK1(7) /* RStCr */ 730 731#define S_RSTCFG_WD 3 /* WBMD */ 732#define M_RSTCFG_WD _MM_MAKEMASK(4,S_RSTCFG_WD) 733#define V_RSTCFG_WD(x) _MM_MAKEVALUE(x,S_RSTCFG_WD) 734#define G_RSTCFG_WD(x) _MM_GETVALUE(x,S_RSTCFG_WD,M_RSTCFG_WD) 735 736#define M_RSTCFG_SS _MM_MAKEMASK1(2) /* SSR */ 737#define M_RSTCFG_SH _MM_MAKEMASK1(1) /* SHR */ 738#define M_RSTCFG_BR _MM_MAKEMASK1(0) /* BdR */ 739 740#endif /* _SB_MIPS32_H */ 741